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Commit 6547fbdb authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Implement WaSetupGtModeTdRowDispatch 



I'm not really sure, since the w/a entry is as thin on details as
ever, and Bspec doesn't say anything about it. But I've figured only
dispatching to rows 0&1 instead of all four should be the right thing
for GT1.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add the missing snb server GT1 to the check, spotted by Chris
Wilson.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4283908e

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -1166,6 +1166,9 @@ struct drm_i915_file_private { 
#define IS_IVB_GT1(dev)		((dev)->pci_device == 0x0156 || \

				 (dev)->pci_device == 0x0152 ||	\

				 (dev)->pci_device == 0x015a)

#define IS_SNB_GT1(dev)		((dev)->pci_device == 0x0102 || \

				 (dev)->pci_device == 0x0106 ||	\

				 (dev)->pci_device == 0x010A)

#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)

#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -534,6 +534,7 @@ 


#define GEN6_GT_MODE	0x20d0

#define   GEN6_GT_MODE_HI				(1 << 9)

#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)



#define GFX_MODE	0x02520

#define GFX_MODE_GEN7	0x0229c

drivers/gpu/drm/i915/intel_pm.c

+5 −0
Original line number Diff line number Diff line
@@ -3596,6 +3596,11 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(_3D_CHICKEN,

		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));



	/* WaSetupGtModeTdRowDispatch */

	if (IS_SNB_GT1(dev))

		I915_WRITE(GEN6_GT_MODE,

			   _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);