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Commit 62f3232d authored by Ajay Agarwal's avatar Ajay Agarwal
Browse files

usb: dwc3: Write necessary registers for dual port enablement 



In line with the sequence for primary port, update proper fields
of DWC3_GUSB2PHYCFG and DWC3_GUSB3PIPECTL registers for the
second port of the dual port controller. Update other registers
as required.
While at it, also avoid enabling SSPHY autosuspend if
dis_u3_susphy_quirk is set.

Change-Id: Ib79dba4c6d854fa2bf33a1b7cecf06f988250662
Signed-off-by: default avatarAjay Agarwal <ajaya@codeaurora.org>
parent 9224f27e

drivers/usb/dwc3/core.c

+32 −0
Original line number Diff line number Diff line
@@ -59,6 +59,9 @@ void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 
{

	u32			reg;



	if (dwc->dis_u3_susphy_quirk)

		return;



	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));



	if (suspend)
@@ -67,6 +70,17 @@ void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 
		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;



	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	if (dwc->dual_port) {

		reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(1));



		if (suspend)

			reg |= DWC3_GUSB3PIPECTL_SUSPHY;

		else

			reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;



		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(1), reg);

	}

}



/**
@@ -143,6 +157,12 @@ void dwc3_en_sleep_mode(struct dwc3 *dwc) 
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	if (dwc->dual_port) {

		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(1));

		reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;

		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(1), reg);

	}

}



void dwc3_dis_sleep_mode(struct dwc3 *dwc)
@@ -565,6 +585,10 @@ static int dwc3_phy_setup(struct dwc3 *dwc) 
	u32 reg;



	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

	if (dwc->dual_port) {

		if (reg != dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(1)))

			dev_warn(dwc->dev, "Reset values of pipectl registers are different!\n");

	}



	/*

	 * Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -616,8 +640,14 @@ static int dwc3_phy_setup(struct dwc3 *dwc) 
				DWC3_GUSB3PIPECTL_P3EXSIGP2);



	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	if (dwc->dual_port)

		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(1), reg);



	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	if (dwc->dual_port) {

		if (reg != dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(1)))

			dev_warn(dwc->dev, "Reset values of usb2phycfg registers are different!\n");

	}



	/* Select the HS PHY interface */

	switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -678,6 +708,8 @@ static int dwc3_phy_setup(struct dwc3 *dwc) 
		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;



	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	if (dwc->dual_port)

		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(1), reg);



	return 0;

}

drivers/usb/dwc3/dwc3-msm.c

+29 −1
Original line number Diff line number Diff line
@@ -2771,6 +2771,14 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc, bool force_power_collapse, 


			reg |= DWC3_GUSB3PIPECTL_DISRXDETU3;

			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



			if (mdwc->dual_port) {

				reg = dwc3_readl(dwc->regs,

						DWC3_GUSB3PIPECTL(1));

				reg |= DWC3_GUSB3PIPECTL_DISRXDETU3;

				dwc3_writel(dwc->regs,

						DWC3_GUSB3PIPECTL(1), reg);

			}

		}

		/* indicate phy about SS mode */

		dwc3_msm_is_superspeed(mdwc);
@@ -2980,6 +2988,14 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) 


			reg &= ~DWC3_GUSB3PIPECTL_DISRXDETU3;

			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



			if (mdwc->dual_port) {

				reg = dwc3_readl(dwc->regs,

						DWC3_GUSB3PIPECTL(1));

				reg &= ~DWC3_GUSB3PIPECTL_DISRXDETU3;

				dwc3_writel(dwc->regs,

						DWC3_GUSB3PIPECTL(1), reg);

			}

		}

	}
@@ -4609,9 +4625,21 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) 
			dwc3_msm_write_reg_field(mdwc->base,

					DWC31_LINK_LU3LFPSRXTIM(0),

					GEN1_U3_EXIT_RSP_RX_CLK_MASK, 5);

			dev_dbg(mdwc->dev, "LU3:%08x\n",

			dev_dbg(mdwc->dev, "link0 LU3:%08x\n",

				dwc3_msm_read_reg(mdwc->base,

					DWC31_LINK_LU3LFPSRXTIM(0)));



			if (mdwc->dual_port) {

				dwc3_msm_write_reg_field(mdwc->base,

					       DWC31_LINK_LU3LFPSRXTIM(1),

					       GEN2_U3_EXIT_RSP_RX_CLK_MASK, 6);

				dwc3_msm_write_reg_field(mdwc->base,

					       DWC31_LINK_LU3LFPSRXTIM(1),

					       GEN1_U3_EXIT_RSP_RX_CLK_MASK, 5);

				dev_dbg(mdwc->dev, "link1 LU3:%08x\n",

					dwc3_msm_read_reg(mdwc->base,

					       DWC31_LINK_LU3LFPSRXTIM(1)));

			}

		}



		/* xHCI should have incremented child count as necessary */