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Commit 5a2564a7 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add coresight dts file for mdm9607"

parents cafb299b 95796c7c

arch/arm64/boot/dts/qcom/mdm9607-coresight.dtsi

+300 −282
Original line number Diff line number Diff line
@@ -12,444 +12,455 @@ 
 */



&soc {

	tmc_etr: tmc@6026000 {

		compatible = "arm,coresight-tmc";

		reg = <0x6026000 0x1000>,

		      <0x6084000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;

		qcom,sg-enable;



		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpiu: tpiu@6020000 {

		compatible = "arm,coresight-tpiu";

		reg = <0x6020000 0x1000>,

		      <0x1100000 0xb0000>;

		reg-names = "tpiu-base", "nidnt-base";



		coresight-id = <1>;

		coresight-name = "coresight-tpiu";

		coresight-nr-inports = <1>;



		pinctrl-names = "sdcard", "trace", "swduart",

				"swdtrc", "jtag", "spmi";

		/* NIDnT */

		pinctrl-0 = <&qdsd_clk_sdcard &qdsd_cmd_sdcard

			     &qdsd_data0_sdcard &qdsd_data1_sdcard

			     &qdsd_data2_sdcard &qdsd_data3_sdcard>;

		pinctrl-1 = <&qdsd_clk_trace &qdsd_cmd_trace

			     &qdsd_data0_trace &qdsd_data1_trace

			     &qdsd_data2_trace &qdsd_data3_trace>;

		pinctrl-2 = <&qdsd_cmd_swduart &qdsd_data0_swduart

			     &qdsd_data1_swduart &qdsd_data2_swduart

			     &qdsd_data3_swduart>;

		pinctrl-3 = <&qdsd_clk_swdtrc &qdsd_cmd_swdtrc

			     &qdsd_data0_swdtrc &qdsd_data1_swdtrc

			     &qdsd_data2_swdtrc &qdsd_data3_swdtrc>;

		pinctrl-4 = <&qdsd_cmd_jtag &qdsd_data0_jtag

			     &qdsd_data1_jtag &qdsd_data2_jtag

			     &qdsd_data3_jtag>;

		pinctrl-5 = <&qdsd_clk_spmi &qdsd_cmd_spmi

			     &qdsd_data0_spmi &qdsd_data3_spmi>;



		qcom,nidnthw;

		qcom,nidnt-swduart;

		qcom,nidnt-swdtrc;

		qcom,nidnt-jtag;

		qcom,nidnt-spmi;

		nidnt-gpio = <26>;

		nidnt-gpio-polarity = <1>;



		interrupts = <0 82 0>;

		interrupt-names = "nidnt-irq";



		vdd-supply = <&sdcard_ext_vreg>;

		qcom,vdd-voltage-level = <2850000 2850000>;

		qcom,vdd-current-level = <15 400000>;



		vdd-io-supply = <&mdm9607_l13>;

		qcom,vdd-io-voltage-level = <1800000 2950000>;

		qcom,vdd-io-current-level = <200 300000>;

	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		coresight-name = "coresight-csr";

		qcom,usb-bam-support;

		qcom,hwctrl-set-support;

		qcom,set-byte-cntr-support;

		qcom,blk-size = <1>;

	};



	replicator: replicator@6024000 {

		compatible = "qcom,coresight-replicator";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b909>;

		reg = <0x6024000 0x1000>;

		reg-names = "replicator-base";



		coresight-id = <2>;

		coresight-name = "coresight-replicator";

		coresight-nr-inports = <1>;

		coresight-outports = <0 1>;

		coresight-child-list = <&tmc_etr &tpiu>;

		coresight-child-ports = <0 0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				replicator_out_tmc_etr: endpoint {

				remote-endpoint=

				<&tmc_etr_in_replicator>;

				};

			};

			port@1 {

				reg = <0>;

				replicator_in_tmc_etf: endpoint {

				slave-mode;

				remote-endpoint =

				<&tmc_etf_out_replicator>;

				};

			};

		};

	};



	tmc_etf: tmc@6025000 {

		compatible = "arm,coresight-tmc";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb961>;

		reg = <0x6025000 0x1000>;

		reg-names = "tmc-base";



		coresight-id = <3>;

		coresight-name = "coresight-tmc-etf";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-csr = <&csr>;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_in0: funnel@6021000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6021000 0x1000>;

		reg-names = "funnel-base";

		clock-names = "apb_pclk","core_a_clk";



		coresight-id = <4>;

		coresight-name = "coresight-funnel-in0";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

			port@0 {

				reg = <0>;

				tmc_etf_out_replicator: endpoint {

					remote-endpoint=

					<&replicator_in_tmc_etf>;

				};

			};

			port@1 {

				reg = <0>;

				tmc_etf_in_funnel_in0: endpoint {

					slave-mode;

					remote-endpoint=

					<&funnel_in0_out_tmc_etf>;

				};

			};

		};

	};



	funnel_in2: funnel@6068000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6068000 0x1000>;

		reg-names = "funnel-base";

	tmc_etr: tmc@6026000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6026000 0x1000>,

			<0x6084000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		qcom,memory-size = <0x100000>;

		qcom,sg-enable;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		coresight-id = <5>;

		coresight-name = "coresight-funnel-in2";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <6>;

		arm,buffer-size = <0x400000>;



		coresight-name = "coresight-tmc-etr";

		coresight-ctis = <&cti0 &cti0>;

		coresight-csr = <&csr>;

		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		port {

			tmc_etr_in_replicator: endpoint {

				slave-mode;

				remote-endpoint =

				<&replicator_out_tmc_etr>;

			};

		};

	};



	cti0: cti@6010000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6010000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <6>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	cti1: cti@6011000 {

		compatible = "arm,coresight-cti";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6011000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <7>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	cti2: cti@6012000 {

		compatible = "arm,coresight-cti";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6012000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <8>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	cti3: cti@6013000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6013000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti4: cti@6014000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6014000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti5: cti@6015000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6015000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti6: cti@6016000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6016000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti7: cti@6017000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6017000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti8: cti@6018000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6018000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti_cpu0: cti@6043000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6043000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		qcom,cti-save;

		cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



	};



	cti_rpm_cpu0: cti@603c000 {

		compatible = "arm,coresight-cti";

		reg = <0x603c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	cti_modem_cpu0: cti@6038000 {

		compatible = "arm,coresight-cti";

		reg = <0x6038000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	stm: stm@6002000 {

		compatible = "arm,coresight-stm";

		reg = <0x6002000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <18>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <7>;

	hwevent: hwevent@606c000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x606c000 0x148>,

			<0x606cfb0 0x4>,

			<0x78640cc 0x4>,

			<0x78240cc 0x4>,

			<0x7885010 0x4>,

			<0x200c004 0x4>,

			<0x78d90a0 0x4>;

		reg-names = "wrapper-mux", "wrapper-lockaccess",

				"wrapper-sdcc2", "wrapper-sdcc1",

				"blsp-mux", "spmi-mux" ,"usb-mux";



		coresight-name = "coresight-hwevent";

		coresight-csr = <&csr>;

		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

	};



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";

	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <19>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		coresight-name = "coresight-rpm-etm0";

		qcom,inst-id = <4>;



		qcom,blk-size = <1>;

		port {

			rpm_etm0_out_funnel_in0: endpoint {

				remote-endpoint =

			<&funnel_in0_in_rpm_etm0>;

			};

		};

	};



	stm: stm@6002000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b962>;

		reg =   <0x6002000 0x1000>,

			<0x09280000 0x180000>;

		reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status";

		coresight-name = "coresight-stm";



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



		port {

			stm_out_funnel_in0: endpoint {

				remote-endpoint = <&funnel_in0_in_stm>;

			};

		};



	etm0: etm@6042000 {

		compatible = "arm,coresight-etm";

		reg = <0x6042000 0x1000>;

		reg-names = "etm-base";

	};



		coresight-id = <20>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU0>;

	funnel_in0: funnel@6021000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b908>;



		reg = <0x6021000 0x1000>;

		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in0";

		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

		clock-names = "apb_pclk","core_a_clk";



	hwevent: hwevent@606c000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x606c000 0x148>,

		      <0x606cfb0 0x4>,

		      <0x78640cc 0x4>,

		      <0x78240cc 0x4>,

		      <0x7885010 0x4>,

		      <0x200c004 0x4>,

		      <0x78d90a0 0x4>;

		reg-names = "wrapper-mux", "wrapper-lockaccess",

			    "wrapper-sdcc2", "wrapper-sdcc1",

			    "blsp-mux", "spmi-mux" ,"usb-mux";

		ports {

			#address-cells = <1>;

			#size-cells = <0>;



		coresight-id = <21>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;

			port@0 {

				reg = <0>;

				funnel_in0_out_tmc_etf: endpoint {

					remote-endpoint=

					<&tmc_etf_in_funnel_in0>;

				};

			};

			port@1 {

				reg = <0>;

				funnel_in0_in_rpm_etm0: endpoint {

					slave-mode;

					remote-endpoint =

				<&rpm_etm0_out_funnel_in0>;

				};

			};

			port@2 {

				reg = <2>;

				funnel_in0_in_modem_etm0: endpoint {

					slave-mode;

					remote-endpoint =

					<&modem_etm0_out_funnel_in0>;

				};

			};

			port@3 {

				reg = <4>;

				funnel_in0_in_etm0: endpoint {

					slave-mode;

					remote-endpoint =

						<&etm0_out_funnel_in0>;

				};

			};

			port@4 {

				reg = <6>;

				funnel_in0_in_funnel_in2: endpoint {

					slave-mode;

					remote-endpoint =

				<&funnel_in2_out_funnel_in0>;

				};

			};

			port@5 {

				reg = <7>;

				funnel_in0_in_stm: endpoint {

					slave-mode;

					remote-endpoint =

					<&stm_out_funnel_in0>;

				};

			};

		};

	};



	funnel_in2: funnel@6068000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6068000 0x1000>;

		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in2";

		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				funnel_in2_out_funnel_in0: endpoint {

					remote-endpoint =

					<&funnel_in0_in_funnel_in2>;

				};

			};



	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";

			port@1 {

				reg = <1>;

				funnel_in2_in_dbgui: endpoint {

					slave-mode;

					remote-endpoint =

					<&dbgui_out_funnel_in2>;

				};

			};

		};

	};



		coresight-id = <22>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;

	etm0: etm@6042000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b956>;

		reg = <0x6042000 0x1000>;

		cpu = <&CPU0>;



		qcom,inst-id = <4>;

		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "apb_pclk","core_a_clk";



		port {

			etm0_out_funnel_in0: endpoint {

				remote-endpoint = <&funnel_in0_in_etm0>;

			};

		};

	};



	modem_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <23>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <2>;



		qcom,inst-id = <2>;

	};



	fuse: fuse@a601c {

		compatible = "arm,coresight-fuse-v2";

		reg = <0xa601c 0x8>;

		reg-names = "fuse-base";



		coresight-id = <24>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

		port {

			modem_etm0_out_funnel_in0: endpoint {

				remote-endpoint =

					<&funnel_in0_in_modem_etm0>;

			};

		};

	};



	dbgui: dbgui@606d000 {

		compatible = "qcom,coresight-dbgui";

		reg = <0x606d000 0x1000>;

		reg-names = "dbgui-base";



		coresight-id = <25>;

		coresight-name = "coresight-dbgui";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in2>;

		coresight-child-ports = <1>;



		qcom,dbgui-addr-offset = <0x30>;

		qcom,dbgui-data-offset = <0xB0>;
@@ -457,6 +468,13 @@ 


		clocks = <&clock_gcc clk_qdss_clk>,

			<&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

		clock-names = "apb_pclk","core_a_clk";

			port {

				dbgui_out_funnel_in2: endpoint {

					remote-endpoint =

				<&funnel_in2_in_dbgui>;

				};

		};

	};



};