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Commit 5868e702 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-smd-rpm: Add snapshot of rpm-smd clocks 



Add snapshot of the clk-smd-rpm driver as of msm-4.4
'commit c5612e341a9f305ad ("DRM: SDE: Fix potential buffer overflow in
SDE encoder").

Change-Id: Icd0d79782ba848ca30c2f53a77307d151ed35534
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent b2bdf7dc

drivers/clk/qcom/clk-smd-rpm.c

+229 −160
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, Linaro Limited

 * Copyright (c) 2014, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -23,10 +23,15 @@ 
#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/soc/qcom/smd-rpm.h>

#include <soc/qcom/rpm-smd.h>

#include <linux/clk.h>



#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/mfd/qcom-rpm.h>



#include "clk-voter.h"

#include "clk-debug.h"



#define QCOM_RPM_KEY_SOFTWARE_ENABLE			0x6e657773

#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY	0x62636370

#define QCOM_RPM_SMD_KEY_RATE				0x007a484b
@@ -37,6 +42,8 @@ 
#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \

			     key)					      \

	static struct clk_smd_rpm _platform##_##_active;		      \

	static unsigned long _name##_##last_active_set_vote;		      \

	static unsigned long _name##_##last_sleep_set_vote;		      \

	static struct clk_smd_rpm _platform##_##_name = {		      \

		.rpm_res_type = (type),					      \

		.rpm_clk_id = (r_id),					      \
@@ -44,9 +51,12 @@ 
		.rpm_key = (key),					      \

		.peer = &_platform##_##_active,				      \

		.rate = INT_MAX,					      \

		.last_active_set_vote = &_name##_##last_active_set_vote,      \

		.last_sleep_set_vote = &_name##_##last_sleep_set_vote,	      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_smd_rpm_ops,			      \

			.name = #_name,					      \

			.flags = CLK_ENABLE_HAND_OFF,			      \

			.parent_names = (const char *[]){ "xo_board" },       \

			.num_parents = 1,				      \

		},							      \
@@ -59,9 +69,12 @@ 
		.rpm_key = (key),					      \

		.peer = &_platform##_##_name,				      \

		.rate = INT_MAX,					      \

		.last_active_set_vote = &_name##_##last_active_set_vote,      \

		.last_sleep_set_vote = &_name##_##last_sleep_set_vote,	      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_smd_rpm_ops,			      \

			.name = #_active,				      \

			.flags = CLK_ENABLE_HAND_OFF,			      \

			.parent_names = (const char *[]){ "xo_board" },	      \

			.num_parents = 1,				      \

		},							      \
@@ -70,6 +83,8 @@ 
#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \

				    stat_id, r, key)			      \

	static struct clk_smd_rpm _platform##_##_active;		      \

	static unsigned long _name##_##last_active_set_vote;		      \

	static unsigned long _name##_##last_sleep_set_vote;		      \

	static struct clk_smd_rpm _platform##_##_name = {		      \

		.rpm_res_type = (type),					      \

		.rpm_clk_id = (r_id),					      \
@@ -78,9 +93,12 @@ 
		.branch = true,						      \

		.peer = &_platform##_##_active,				      \

		.rate = (r),						      \

		.last_active_set_vote = &_name##_##last_active_set_vote,      \

		.last_sleep_set_vote = &_name##_##last_sleep_set_vote,	      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_smd_rpm_branch_ops,			      \

			.name = #_name,					      \

			.flags = CLK_ENABLE_HAND_OFF,			      \

			.parent_names = (const char *[]){ "xo_board" },	      \

			.num_parents = 1,				      \

		},							      \
@@ -94,9 +112,12 @@ 
		.branch = true,						      \

		.peer = &_platform##_##_name,				      \

		.rate = (r),						      \

		.last_active_set_vote = &_name##_##last_active_set_vote,      \

		.last_sleep_set_vote = &_name##_##last_sleep_set_vote,	      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_smd_rpm_branch_ops,			      \

			.name = #_active,				      \

			.flags = CLK_ENABLE_HAND_OFF,			      \

			.parent_names = (const char *[]){ "xo_board" },	      \

			.num_parents = 1,				      \

		},							      \
@@ -137,7 +158,8 @@ struct clk_smd_rpm { 
	struct clk_smd_rpm *peer;

	struct clk_hw hw;

	unsigned long rate;

	struct qcom_smd_rpm *rpm;

	unsigned long *last_active_set_vote;

	unsigned long *last_sleep_set_vote;

};



struct clk_smd_rpm_req {
@@ -148,72 +170,76 @@ struct clk_smd_rpm_req { 


struct rpm_cc {

	struct qcom_rpm *rpm;

	struct clk_smd_rpm **clks;

	size_t num_clks;

	struct clk_onecell_data data;

	struct clk *clks[];

};



struct rpm_smd_clk_desc {

	struct clk_smd_rpm **clks;

	struct clk_hw **clks;

	size_t num_rpm_clks;

	size_t num_clks;

};



static DEFINE_MUTEX(rpm_smd_clk_lock);



static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)

static int clk_smd_rpm_prepare(struct clk_hw *hw);



static int clk_smd_rpm_handoff(struct clk_hw *hw)

{

	int ret;

	struct clk_smd_rpm_req req = {

	return clk_smd_rpm_prepare(hw);

}



static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,

					uint32_t rate)

{

	int ret = 0;

	struct msm_rpm_kvp req = {

		.key = cpu_to_le32(r->rpm_key),

		.nbytes = cpu_to_le32(sizeof(u32)),

		.value = cpu_to_le32(r->branch ? 1 : INT_MAX),

		.data = (void *)&rate,

		.length = sizeof(rate),

	};



	ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,

				 r->rpm_res_type, r->rpm_clk_id, &req,

				 sizeof(req));

	if (ret)

	if (*r->last_active_set_vote == rate)

		return ret;

	ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,

				 r->rpm_res_type, r->rpm_clk_id, &req,

				 sizeof(req));



	ret = msm_rpm_send_message(QCOM_SMD_RPM_ACTIVE_STATE, r->rpm_res_type,

			r->rpm_clk_id, &req, 1);

	if (ret)

		return ret;



	return 0;

}



static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,

				       unsigned long rate)

{

	struct clk_smd_rpm_req req = {

		.key = cpu_to_le32(r->rpm_key),

		.nbytes = cpu_to_le32(sizeof(u32)),

		.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */

	};

	*r->last_active_set_vote = rate;



	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,

				  r->rpm_res_type, r->rpm_clk_id, &req,

				  sizeof(req));

	return ret;

}



static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,

				      unsigned long rate)

					uint32_t rate)

{

	struct clk_smd_rpm_req req = {

	int ret = 0;

	struct msm_rpm_kvp req = {

		.key = cpu_to_le32(r->rpm_key),

		.nbytes = cpu_to_le32(sizeof(u32)),

		.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */

		.data = (void *)&rate,

		.length = sizeof(rate),

	};



	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,

				  r->rpm_res_type, r->rpm_clk_id, &req,

				  sizeof(req));

	if (*r->last_sleep_set_vote == rate)

		return ret;



	ret = msm_rpm_send_message(QCOM_SMD_RPM_SLEEP_STATE, r->rpm_res_type,

			r->rpm_clk_id, &req, 1);

	if (ret)

		return ret;



	*r->last_sleep_set_vote = rate;



	return ret;

}



static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,

			    unsigned long *active, unsigned long *sleep)

{

	*active = rate;

	/* Convert the rate (hz) to khz */

	*active = DIV_ROUND_UP(rate, 1000);



	/*

	 * Active-only clocks don't care what the rate is during sleep. So,
@@ -231,17 +257,17 @@ static int clk_smd_rpm_prepare(struct clk_hw *hw) 
	struct clk_smd_rpm *peer = r->peer;

	unsigned long this_rate = 0, this_sleep_rate = 0;

	unsigned long peer_rate = 0, peer_sleep_rate = 0;

	unsigned long active_rate, sleep_rate;

	uint32_t active_rate, sleep_rate;

	int ret = 0;



	mutex_lock(&rpm_smd_clk_lock);



	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);



	/* Don't send requests to the RPM if the rate has not been set. */

	if (!r->rate)

	if (this_rate == 0)

		goto out;



	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);



	/* Take peer clock's rate into account only if it's enabled. */

	if (peer->enabled)

		to_active_sleep(peer, peer->rate,
@@ -279,13 +305,13 @@ static void clk_smd_rpm_unprepare(struct clk_hw *hw) 
	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);

	struct clk_smd_rpm *peer = r->peer;

	unsigned long peer_rate = 0, peer_sleep_rate = 0;

	unsigned long active_rate, sleep_rate;

	uint32_t active_rate, sleep_rate;

	int ret;



	mutex_lock(&rpm_smd_clk_lock);



	if (!r->rate)

		goto out;

		goto enable;



	/* Take peer clock's rate into account only if it's enabled. */

	if (peer->enabled)
@@ -302,6 +328,7 @@ static void clk_smd_rpm_unprepare(struct clk_hw *hw) 
	if (ret)

		goto out;



enable:

	r->enabled = false;



out:
@@ -313,7 +340,7 @@ static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);

	struct clk_smd_rpm *peer = r->peer;

	unsigned long active_rate, sleep_rate;

	uint32_t active_rate, sleep_rate;

	unsigned long this_rate = 0, this_sleep_rate = 0;

	unsigned long peer_rate = 0, peer_sleep_rate = 0;

	int ret = 0;
@@ -372,33 +399,62 @@ static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 
	return r->rate;

}



static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)

static int clk_smd_rpm_enable_scaling(void)

{

	int ret;

	struct clk_smd_rpm_req req = {

	int ret = 0;

	uint32_t value = cpu_to_le32(1);

	struct msm_rpm_kvp req = {

		.key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),

		.nbytes = cpu_to_le32(sizeof(u32)),

		.value = cpu_to_le32(1),

		.data = (void *)&value,

		.length = sizeof(value),

	};



	ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,

	ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_SLEEP_STATE,

			QCOM_SMD_RPM_MISC_CLK,

				 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));

			QCOM_RPM_SCALING_ENABLE_ID, &req, 1);

	if (ret) {

		pr_err("RPM clock scaling (sleep set) not enabled!\n");

		return ret;

	}



	ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,

	ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_ACTIVE_STATE,

			QCOM_SMD_RPM_MISC_CLK,

				 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));

			QCOM_RPM_SCALING_ENABLE_ID, &req, 1);

	if (ret) {

		pr_err("RPM clock scaling (active set) not enabled!\n");

		return ret;

	}



	pr_debug("%s: RPM clock scaling is enabled\n", __func__);

	return 0;

	return ret;

}



static int clk_vote_bimc(struct clk_hw *hw, uint32_t rate)

{

	int ret = 0;

	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);

	struct msm_rpm_kvp req = {

		.key = r->rpm_key,

		.data = (void *)&rate,

		.length = sizeof(rate),

	};



	ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_ACTIVE_STATE,

		r->rpm_res_type, r->rpm_clk_id, &req, 1);

	if (ret < 0) {

		if (ret != -EPROBE_DEFER)

			WARN(1, "BIMC vote not sent!\n");

		return ret;

	}



	return ret;

}



static int clk_smd_rpm_is_enabled(struct clk_hw *hw)

{

	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);



	return r->enabled;

}



static const struct clk_ops clk_smd_rpm_ops = {
@@ -407,11 +463,17 @@ static const struct clk_ops clk_smd_rpm_ops = { 
	.set_rate	= clk_smd_rpm_set_rate,

	.round_rate	= clk_smd_rpm_round_rate,

	.recalc_rate	= clk_smd_rpm_recalc_rate,

	.is_enabled	= clk_smd_rpm_is_enabled,

	.debug_init	= clk_debug_measure_add,

};



static const struct clk_ops clk_smd_rpm_branch_ops = {

	.prepare	= clk_smd_rpm_prepare,

	.unprepare	= clk_smd_rpm_unprepare,

	.round_rate	= clk_smd_rpm_round_rate,

	.recalc_rate	= clk_smd_rpm_recalc_rate,

	.is_enabled	= clk_smd_rpm_is_enabled,

	.debug_init	= clk_debug_measure_add,

};



/* msm8916 */
@@ -428,35 +490,36 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2); 
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);



static struct clk_smd_rpm *msm8916_clks[] = {

	[RPM_SMD_PCNOC_CLK]		= &msm8916_pcnoc_clk,

	[RPM_SMD_PCNOC_A_CLK]		= &msm8916_pcnoc_a_clk,

	[RPM_SMD_SNOC_CLK]		= &msm8916_snoc_clk,

	[RPM_SMD_SNOC_A_CLK]		= &msm8916_snoc_a_clk,

	[RPM_SMD_BIMC_CLK]		= &msm8916_bimc_clk,

	[RPM_SMD_BIMC_A_CLK]		= &msm8916_bimc_a_clk,

	[RPM_SMD_QDSS_CLK]		= &msm8916_qdss_clk,

	[RPM_SMD_QDSS_A_CLK]		= &msm8916_qdss_a_clk,

	[RPM_SMD_BB_CLK1]		= &msm8916_bb_clk1,

	[RPM_SMD_BB_CLK1_A]		= &msm8916_bb_clk1_a,

	[RPM_SMD_BB_CLK2]		= &msm8916_bb_clk2,

	[RPM_SMD_BB_CLK2_A]		= &msm8916_bb_clk2_a,

	[RPM_SMD_RF_CLK1]		= &msm8916_rf_clk1,

	[RPM_SMD_RF_CLK1_A]		= &msm8916_rf_clk1_a,

	[RPM_SMD_RF_CLK2]		= &msm8916_rf_clk2,

	[RPM_SMD_RF_CLK2_A]		= &msm8916_rf_clk2_a,

	[RPM_SMD_BB_CLK1_PIN]		= &msm8916_bb_clk1_pin,

	[RPM_SMD_BB_CLK1_A_PIN]		= &msm8916_bb_clk1_a_pin,

	[RPM_SMD_BB_CLK2_PIN]		= &msm8916_bb_clk2_pin,

	[RPM_SMD_BB_CLK2_A_PIN]		= &msm8916_bb_clk2_a_pin,

	[RPM_SMD_RF_CLK1_PIN]		= &msm8916_rf_clk1_pin,

	[RPM_SMD_RF_CLK1_A_PIN]		= &msm8916_rf_clk1_a_pin,

	[RPM_SMD_RF_CLK2_PIN]		= &msm8916_rf_clk2_pin,

	[RPM_SMD_RF_CLK2_A_PIN]		= &msm8916_rf_clk2_a_pin,

static struct clk_hw *msm8916_clks[] = {

	[RPM_SMD_PCNOC_CLK]		= &msm8916_pcnoc_clk.hw,

	[RPM_SMD_PCNOC_A_CLK]		= &msm8916_pcnoc_a_clk.hw,

	[RPM_SMD_SNOC_CLK]		= &msm8916_snoc_clk.hw,

	[RPM_SMD_SNOC_A_CLK]		= &msm8916_snoc_a_clk.hw,

	[RPM_SMD_BIMC_CLK]		= &msm8916_bimc_clk.hw,

	[RPM_SMD_BIMC_A_CLK]		= &msm8916_bimc_a_clk.hw,

	[RPM_SMD_QDSS_CLK]		= &msm8916_qdss_clk.hw,

	[RPM_SMD_QDSS_A_CLK]		= &msm8916_qdss_a_clk.hw,

	[RPM_SMD_BB_CLK1]		= &msm8916_bb_clk1.hw,

	[RPM_SMD_BB_CLK1_A]		= &msm8916_bb_clk1_a.hw,

	[RPM_SMD_BB_CLK2]		= &msm8916_bb_clk2.hw,

	[RPM_SMD_BB_CLK2_A]		= &msm8916_bb_clk2_a.hw,

	[RPM_SMD_RF_CLK1]		= &msm8916_rf_clk1.hw,

	[RPM_SMD_RF_CLK1_A]		= &msm8916_rf_clk1_a.hw,

	[RPM_SMD_RF_CLK2]		= &msm8916_rf_clk2.hw,

	[RPM_SMD_RF_CLK2_A]		= &msm8916_rf_clk2_a.hw,

	[RPM_SMD_BB_CLK1_PIN]		= &msm8916_bb_clk1_pin.hw,

	[RPM_SMD_BB_CLK1_A_PIN]		= &msm8916_bb_clk1_a_pin.hw,

	[RPM_SMD_BB_CLK2_PIN]		= &msm8916_bb_clk2_pin.hw,

	[RPM_SMD_BB_CLK2_A_PIN]		= &msm8916_bb_clk2_a_pin.hw,

	[RPM_SMD_RF_CLK1_PIN]		= &msm8916_rf_clk1_pin.hw,

	[RPM_SMD_RF_CLK1_A_PIN]		= &msm8916_rf_clk1_a_pin.hw,

	[RPM_SMD_RF_CLK2_PIN]		= &msm8916_rf_clk2_pin.hw,

	[RPM_SMD_RF_CLK2_A_PIN]		= &msm8916_rf_clk2_a_pin.hw,

};



static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {

	.clks = msm8916_clks,

	.num_rpm_clks = RPM_RF_CLK2_A_PIN,

	.num_clks = ARRAY_SIZE(msm8916_clks),

};
@@ -483,53 +546,55 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4); 
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);



static struct clk_smd_rpm *msm8974_clks[] = {

	[RPM_SMD_PNOC_CLK]		= &msm8974_pnoc_clk,

	[RPM_SMD_PNOC_A_CLK]		= &msm8974_pnoc_a_clk,

	[RPM_SMD_SNOC_CLK]		= &msm8974_snoc_clk,

	[RPM_SMD_SNOC_A_CLK]		= &msm8974_snoc_a_clk,

	[RPM_SMD_CNOC_CLK]		= &msm8974_cnoc_clk,

	[RPM_SMD_CNOC_A_CLK]		= &msm8974_cnoc_a_clk,

	[RPM_SMD_MMSSNOC_AHB_CLK]	= &msm8974_mmssnoc_ahb_clk,

	[RPM_SMD_MMSSNOC_AHB_A_CLK]	= &msm8974_mmssnoc_ahb_a_clk,

	[RPM_SMD_BIMC_CLK]		= &msm8974_bimc_clk,

	[RPM_SMD_BIMC_A_CLK]		= &msm8974_bimc_a_clk,

	[RPM_SMD_OCMEMGX_CLK]		= &msm8974_ocmemgx_clk,

	[RPM_SMD_OCMEMGX_A_CLK]		= &msm8974_ocmemgx_a_clk,

	[RPM_SMD_QDSS_CLK]		= &msm8974_qdss_clk,

	[RPM_SMD_QDSS_A_CLK]		= &msm8974_qdss_a_clk,

	[RPM_SMD_CXO_D0]		= &msm8974_cxo_d0,

	[RPM_SMD_CXO_D0_A]		= &msm8974_cxo_d0_a,

	[RPM_SMD_CXO_D1]		= &msm8974_cxo_d1,

	[RPM_SMD_CXO_D1_A]		= &msm8974_cxo_d1_a,

	[RPM_SMD_CXO_A0]		= &msm8974_cxo_a0,

	[RPM_SMD_CXO_A0_A]		= &msm8974_cxo_a0_a,

	[RPM_SMD_CXO_A1]		= &msm8974_cxo_a1,

	[RPM_SMD_CXO_A1_A]		= &msm8974_cxo_a1_a,

	[RPM_SMD_CXO_A2]		= &msm8974_cxo_a2,

	[RPM_SMD_CXO_A2_A]		= &msm8974_cxo_a2_a,

	[RPM_SMD_DIFF_CLK]		= &msm8974_diff_clk,

	[RPM_SMD_DIFF_A_CLK]		= &msm8974_diff_a_clk,

	[RPM_SMD_DIV_CLK1]		= &msm8974_div_clk1,

	[RPM_SMD_DIV_A_CLK1]		= &msm8974_div_a_clk1,

	[RPM_SMD_DIV_CLK2]		= &msm8974_div_clk2,

	[RPM_SMD_DIV_A_CLK2]		= &msm8974_div_a_clk2,

	[RPM_SMD_CXO_D0_PIN]		= &msm8974_cxo_d0_pin,

	[RPM_SMD_CXO_D0_A_PIN]		= &msm8974_cxo_d0_a_pin,

	[RPM_SMD_CXO_D1_PIN]		= &msm8974_cxo_d1_pin,

	[RPM_SMD_CXO_D1_A_PIN]		= &msm8974_cxo_d1_a_pin,

	[RPM_SMD_CXO_A0_PIN]		= &msm8974_cxo_a0_pin,

	[RPM_SMD_CXO_A0_A_PIN]		= &msm8974_cxo_a0_a_pin,

	[RPM_SMD_CXO_A1_PIN]		= &msm8974_cxo_a1_pin,

	[RPM_SMD_CXO_A1_A_PIN]		= &msm8974_cxo_a1_a_pin,

	[RPM_SMD_CXO_A2_PIN]		= &msm8974_cxo_a2_pin,

	[RPM_SMD_CXO_A2_A_PIN]		= &msm8974_cxo_a2_a_pin,

static struct clk_hw *msm8974_clks[] = {

	[RPM_SMD_PNOC_CLK]		= &msm8974_pnoc_clk.hw,

	[RPM_SMD_PNOC_A_CLK]		= &msm8974_pnoc_a_clk.hw,

	[RPM_SMD_SNOC_CLK]		= &msm8974_snoc_clk.hw,

	[RPM_SMD_SNOC_A_CLK]		= &msm8974_snoc_a_clk.hw,

	[RPM_SMD_CNOC_CLK]		= &msm8974_cnoc_clk.hw,

	[RPM_SMD_CNOC_A_CLK]		= &msm8974_cnoc_a_clk.hw,

	[RPM_SMD_MMSSNOC_AHB_CLK]	= &msm8974_mmssnoc_ahb_clk.hw,

	[RPM_SMD_MMSSNOC_AHB_A_CLK]	= &msm8974_mmssnoc_ahb_a_clk.hw,

	[RPM_SMD_BIMC_CLK]		= &msm8974_bimc_clk.hw,

	[RPM_SMD_BIMC_A_CLK]		= &msm8974_bimc_a_clk.hw,

	[RPM_SMD_OCMEMGX_CLK]		= &msm8974_ocmemgx_clk.hw,

	[RPM_SMD_OCMEMGX_A_CLK]		= &msm8974_ocmemgx_a_clk.hw,

	[RPM_SMD_QDSS_CLK]		= &msm8974_qdss_clk.hw,

	[RPM_SMD_QDSS_A_CLK]		= &msm8974_qdss_a_clk.hw,

	[RPM_SMD_CXO_D0]		= &msm8974_cxo_d0.hw,

	[RPM_SMD_CXO_D0_A]		= &msm8974_cxo_d0_a.hw,

	[RPM_SMD_CXO_D1]		= &msm8974_cxo_d1.hw,

	[RPM_SMD_CXO_D1_A]		= &msm8974_cxo_d1_a.hw,

	[RPM_SMD_CXO_A0]		= &msm8974_cxo_a0.hw,

	[RPM_SMD_CXO_A0_A]		= &msm8974_cxo_a0_a.hw,

	[RPM_SMD_CXO_A1]		= &msm8974_cxo_a1.hw,

	[RPM_SMD_CXO_A1_A]		= &msm8974_cxo_a1_a.hw,

	[RPM_SMD_CXO_A2]		= &msm8974_cxo_a2.hw,

	[RPM_SMD_CXO_A2_A]		= &msm8974_cxo_a2_a.hw,

	[RPM_SMD_DIFF_CLK]		= &msm8974_diff_clk.hw,

	[RPM_SMD_DIFF_A_CLK]		= &msm8974_diff_a_clk.hw,

	[RPM_SMD_DIV_CLK1]		= &msm8974_div_clk1.hw,

	[RPM_SMD_DIV_A_CLK1]		= &msm8974_div_a_clk1.hw,

	[RPM_SMD_DIV_CLK2]		= &msm8974_div_clk2.hw,

	[RPM_SMD_DIV_A_CLK2]		= &msm8974_div_a_clk2.hw,

	[RPM_SMD_CXO_D0_PIN]		= &msm8974_cxo_d0_pin.hw,

	[RPM_SMD_CXO_D0_A_PIN]		= &msm8974_cxo_d0_a_pin.hw,

	[RPM_SMD_CXO_D1_PIN]		= &msm8974_cxo_d1_pin.hw,

	[RPM_SMD_CXO_D1_A_PIN]		= &msm8974_cxo_d1_a_pin.hw,

	[RPM_SMD_CXO_A0_PIN]		= &msm8974_cxo_a0_pin.hw,

	[RPM_SMD_CXO_A0_A_PIN]		= &msm8974_cxo_a0_a_pin.hw,

	[RPM_SMD_CXO_A1_PIN]		= &msm8974_cxo_a1_pin.hw,

	[RPM_SMD_CXO_A1_A_PIN]		= &msm8974_cxo_a1_a_pin.hw,

	[RPM_SMD_CXO_A2_PIN]		= &msm8974_cxo_a2_pin.hw,

	[RPM_SMD_CXO_A2_A_PIN]		= &msm8974_cxo_a2_a_pin.hw,

};



static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {

	.clks = msm8974_clks,

	.num_rpm_clks = RPM_SMD_CXO_A2_A_PIN,

	.num_clks = ARRAY_SIZE(msm8974_clks),

};



static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
@@ -537,78 +602,82 @@ static const struct of_device_id rpm_smd_clk_match_table[] = { 
};

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);



static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,

					     void *data)

{

	struct rpm_cc *rcc = data;

	unsigned int idx = clkspec->args[0];



	if (idx >= rcc->num_clks) {

		pr_err("%s: invalid index %u\n", __func__, idx);

		return ERR_PTR(-EINVAL);

	}



	return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);

}



static int rpm_smd_clk_probe(struct platform_device *pdev)

{

	struct clk **clks;

	struct clk *clk;

	struct rpm_cc *rcc;

	struct clk_onecell_data *data;

	int ret;

	size_t num_clks, i;

	struct qcom_smd_rpm *rpm;

	struct clk_smd_rpm **rpm_smd_clks;

	struct clk_hw **hw_clks;

	const struct rpm_smd_clk_desc *desc;



	rpm = dev_get_drvdata(pdev->dev.parent);

	if (!rpm) {

		dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");

		return -ENODEV;

	}



	desc = of_device_get_match_data(&pdev->dev);

	if (!desc)

		return -EINVAL;



	rpm_smd_clks = desc->clks;

	hw_clks = desc->clks;

	num_clks = desc->num_clks;



	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);

	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*clks) * num_clks,

			   GFP_KERNEL);

	if (!rcc)

		return -ENOMEM;



	rcc->clks = rpm_smd_clks;

	rcc->num_clks = num_clks;

	clks = rcc->clks;

	data = &rcc->data;

	data->clks = clks;

	data->clk_num = num_clks;



	for (i = 0; i < num_clks; i++) {

		if (!rpm_smd_clks[i])

	for (i = 0; i <= desc->num_rpm_clks; i++) {

		if (!hw_clks[i]) {

			clks[i] = ERR_PTR(-ENOENT);

			continue;

		}



		rpm_smd_clks[i]->rpm = rpm;

		ret = clk_smd_rpm_handoff(hw_clks[i]);

		if (ret)

			goto err;

	}



		ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);

	for (i = (desc->num_rpm_clks + 1); i < num_clks; i++) {

		if (!hw_clks[i]) {

			clks[i] = ERR_PTR(-ENOENT);

			continue;

		}



		ret = voter_clk_handoff(hw_clks[i]);

		if (ret)

			goto err;

	}



	ret = clk_smd_rpm_enable_scaling(rpm);

	ret = clk_smd_rpm_enable_scaling();

	if (ret)

		goto err;



	for (i = 0; i < num_clks; i++) {

		if (!rpm_smd_clks[i])

		if (!hw_clks[i]) {

			clks[i] = ERR_PTR(-ENOENT);

			continue;

		}



		ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);

		if (ret)

		clk = devm_clk_register(&pdev->dev, hw_clks[i]);

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);

			goto err;

		}



	ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_smdrpm_clk_hw_get,

				     rcc);

		clks[i] = clk;

	}



	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,

				  data);

	if (ret)

		goto err;



	dev_info(&pdev->dev, "Registered RPM clocks\n");



	return 0;

err:

	dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);