Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 580041f9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: npucc: Add pll config for NPU Q6 PLL"

parents d349ead5 d41a54a6

drivers/clk/qcom/npucc-atoll.c

+21 −4
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static const char * const npu_cc_parent_names_1[] = { 


static const struct parent_map npu_cc_parent_map_2[] = {

	{ P_BI_TCXO, 0 },

	{ P_NPU_Q6SS_PLL_OUT_MAIN, 1 },

	{ P_NPU_Q6SS_PLL_OUT_MAIN, 2 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};
@@ -118,7 +118,7 @@ static struct pll_vco fabia_vco[] = { 
	{ 125000000, 1000000000, 1 },

};



static const struct alpha_pll_config npu_cc_pll0_config = {

static struct alpha_pll_config npu_cc_pll0_config = {

	.l = 0x1C,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002067,
@@ -132,6 +132,7 @@ static struct clk_alpha_pll npu_cc_pll0 = { 
	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.config = &npu_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_pll0",
@@ -169,7 +170,7 @@ static struct clk_alpha_pll_postdiv npu_cc_pll0_out_even = { 
	},

};



static const struct alpha_pll_config npu_cc_pll1_config = {

static struct alpha_pll_config npu_cc_pll1_config = {

	.l = 0xF,

	.frac = 0xA000,

	.config_ctl_val = 0x20485699,
@@ -184,6 +185,7 @@ static struct clk_alpha_pll npu_cc_pll1 = { 
	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.config = &npu_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_pll1",
@@ -221,7 +223,7 @@ static struct clk_alpha_pll_postdiv npu_cc_pll1_out_even = { 
	},

};



static const struct alpha_pll_config npu_q6ss_pll_config = {

static struct alpha_pll_config npu_q6ss_pll_config = {

	.l = 0xD,

	.frac = 0x555,

	.config_ctl_val = 0x20485699,
@@ -236,6 +238,7 @@ static struct clk_alpha_pll npu_q6ss_pll = { 
	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.config = &npu_q6ss_pll_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "npu_q6ss_pll",
@@ -341,6 +344,7 @@ static const struct freq_tbl ftbl_npu_dsp_core_clk_src[] = { 
	F(300000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(400000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(500000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(600000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(660000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(800000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	{ }
@@ -352,6 +356,7 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { 
	.hid_width = 5,

	.parent_map = npu_cc_parent_map_2,

	.freq_tbl = ftbl_npu_dsp_core_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "npu_dsp_core_clk_src",

		.parent_names = npu_cc_parent_names_2,
@@ -525,6 +530,10 @@ static struct clk_branch npu_cc_dsp_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_dsp_axi_clk",

			.parent_names = (const char *[]){

				"gcc_npu_axi_clk"

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -551,6 +560,10 @@ static struct clk_branch npu_cc_noc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_noc_axi_clk",

			.parent_names = (const char *[]){

				"gcc_npu_axi_clk"

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -564,6 +577,10 @@ static struct clk_branch npu_cc_noc_dma_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_noc_dma_clk",

			.parent_names = (const char *[]){

				"gcc_npu_dma_clk"

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

include/dt-bindings/clock/qcom,npucc-atoll.h

+21 −22
Original line number Diff line number Diff line
@@ -19,28 +19,27 @@ 
#define NPU_CC_PLL0_OUT_EVEN					1

#define NPU_CC_PLL1						2

#define NPU_CC_PLL1_OUT_EVEN					3

#define NPU_Q6SS_PLL						4

#define NPU_Q6SS_PLL_OUT_EVEN					5

#define NPU_CC_AON_CLK						6

#define NPU_CC_ATB_CLK						7

#define NPU_CC_BTO_CORE_CLK					8

#define NPU_CC_BWMON_CLK					9

#define NPU_CC_CAL_HM0_CDC_CLK					10

#define NPU_CC_CAL_HM0_CLK					11

#define NPU_CC_CAL_HM0_CLK_SRC					12

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				13

#define NPU_CC_CORE_CLK						14

#define NPU_CC_CORE_CLK_SRC					15

#define NPU_CC_DSP_AHBM_CLK					16

#define NPU_CC_DSP_AHBS_CLK					17

#define NPU_CC_DSP_AXI_CLK					18

#define NPU_CC_NOC_AHB_CLK					19

#define NPU_CC_NOC_AXI_CLK					20

#define NPU_CC_NOC_DMA_CLK					21

#define NPU_CC_RSC_XO_CLK					22

#define NPU_CC_S2P_CLK						23

#define NPU_CC_XO_CLK						24

#define NPU_DSP_CORE_CLK_SRC					25

#define NPU_CC_AON_CLK						4

#define NPU_CC_ATB_CLK						5

#define NPU_CC_BTO_CORE_CLK					6

#define NPU_CC_BWMON_CLK					7

#define NPU_CC_CAL_HM0_CDC_CLK					8

#define NPU_CC_CAL_HM0_CLK					9

#define NPU_CC_CAL_HM0_CLK_SRC					10

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				11

#define NPU_CC_CORE_CLK						12

#define NPU_CC_CORE_CLK_SRC					13

#define NPU_CC_DSP_AHBM_CLK					14

#define NPU_CC_DSP_AHBS_CLK					15

#define NPU_CC_DSP_AXI_CLK					16

#define NPU_CC_NOC_AHB_CLK					17

#define NPU_CC_NOC_AXI_CLK					18

#define NPU_CC_NOC_DMA_CLK					19

#define NPU_CC_RSC_XO_CLK					20

#define NPU_CC_S2P_CLK						21

#define NPU_CC_XO_CLK						22

#define NPU_DSP_CORE_CLK_SRC					23

#define NPU_Q6SS_PLL						24



/* NPU_CC resets */

#define NPU_CC_CAL_HM0_BCR					0