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Commit 5584b4da authored by Max Filippov's avatar Max Filippov Committed by Chris Zankel
Browse files

xtensa: add XTFPGA DTS 



Add common XTFPGA parts as *.dtsi (base board, flash) and DTS for LX60
and for ML605.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent 0d456bad

arch/xtensa/boot/dts/lx60.dts

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/dts-v1/;

/include/ "xtfpga.dtsi"

/include/ "xtfpga-flash-4m.dtsi"



/ {

	compatible = "xtensa,lx60";

	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x04000000>;

	};

};

arch/xtensa/boot/dts/ml605.dts

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/dts-v1/;

/include/ "xtfpga.dtsi"

/include/ "xtfpga-flash-16m.dtsi"



/ {

	compatible = "xtensa,ml605";

	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x08000000>;

	};

};

arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi

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/ {

	flash: flash@f8000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cfi-flash";

		reg = <0xf8000000 0x01000000>;

		bank-width = <2>;

		device-width = <2>;

		partition@0x0 {

			label = "boot loader area";

			reg = <0x00000000 0x00400000>;

		};

		partition@0x400000 {

			label = "kernel image";

			reg = <0x00400000 0x00600000>;

		};

		partition@0xa00000 {

			label = "data";

			reg = <0x00a00000 0x005e0000>;

		};

		partition@0xfe0000 {

			label = "boot environment";

			reg = <0x00fe0000 0x00020000>;

		};

        };

};

arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi

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/ {

	flash: flash@f8000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cfi-flash";

		reg = <0xf8000000 0x00400000>;

		bank-width = <2>;

		device-width = <2>;

		partition@0x0 {

			label = "boot loader area";

			reg = <0x00000000 0x003f0000>;

		};

		partition@0x3f0000 {

			label = "boot environment";

			reg = <0x003f0000 0x00010000>;

		};

        };

};

arch/xtensa/boot/dts/xtfpga.dtsi

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/ {

	compatible = "xtensa,xtfpga";

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&pic>;



	chosen {

		bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x06000000>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu@0 {

			compatible = "xtensa,cpu";

			reg = <0>;

			/* Filled in by platform_setup from FPGA register

			 * clock-frequency = <100000000>;

			 */

		};

	};



	pic: pic {

		compatible = "xtensa,pic";

		/* one cell: internal irq number,

		 * two cells: second cell == 0: internal irq number

		 *            second cell == 1: external irq number

		 */

		#interrupt-cells = <2>;

		interrupt-controller;

	};



	serial0: serial@fd050020 {

		device_type = "serial";

		compatible = "ns16550a";

		no-loopback-test;

		reg = <0xfd050020 0x20>;

		reg-shift = <2>;

		interrupts = <0 1>; /* external irq 0 */

		/* Filled in by platform_setup from FPGA register

		 * clock-frequency = <100000000>;

		 */

	};



	enet0: ethoc@fd030000 {

		compatible = "opencores,ethoc";

		reg = <0xfd030000 0x4000 0xfd800000 0x4000>;

		interrupts = <1 1>; /* external irq 1 */

		local-mac-address = [00 50 c2 13 6f 00];

	};

};