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Commit 4f52f6cf authored by Avaneesh Kumar Dwivedi's avatar Avaneesh Kumar Dwivedi Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Change mem timer base for qcs405 



The base of mem timer was incorrect, resulting
in non firing of mem timer hence updating the same.

Change-Id: Ib62a1599abf554f01af63b2f26aa994e12824ac8
Signed-off-by: default avatarAvaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Signed-off-by: default avatarArchit Saxena <archsaxe@codeaurora.org>
parent ac121119

arch/arm64/boot/dts/qcom/qcs405.dtsi

+18 −18
Original line number Original line Diff line number Diff line
@@ -26,7 +26,7 @@ 
	interrupt-parent = <&intc>;

	interrupt-parent = <&intc>;





	chosen {

	chosen {

		bootargs = "sched_enable_hmp=1";

		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";

	};

	};





	reserved-memory {

	reserved-memory {
@@ -139,61 +139,61 @@ 
		clock-frequency = <19200000>;

		clock-frequency = <19200000>;

	};

	};





	timer@b020000 {

	timer@b120000 {

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		ranges;

		ranges;

		compatible = "arm,armv7-timer-mem";

		compatible = "arm,armv7-timer-mem";

		reg = <0xb020000 0x1000>;

		reg = <0xb120000 0x1000>;

		clock-frequency = <19200000>;

		clock-frequency = <19200000>;





		frame@b021000 {

		frame@b121000 {

			frame-number = <0>;

			frame-number = <0>;

			interrupts = <0 8 0x4>,

			interrupts = <0 8 0x4>,

				     <0 7 0x4>;

				     <0 7 0x4>;

			reg = <0xb021000 0x1000>,

			reg = <0xb121000 0x1000>,

			      <0xb022000 0x1000>;

			      <0xb122000 0x1000>;

		};

		};





		frame@b023000 {

		frame@b123000 {

			frame-number = <1>;

			frame-number = <1>;

			interrupts = <0 9 0x4>;

			interrupts = <0 9 0x4>;

			reg = <0xb023000 0x1000>;

			reg = <0xb123000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};





		frame@b024000 {

		frame@b124000 {

			frame-number = <2>;

			frame-number = <2>;

			interrupts = <0 10 0x4>;

			interrupts = <0 10 0x4>;

			reg = <0xb024000 0x1000>;

			reg = <0xb124000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};





		frame@b025000 {

		frame@b125000 {

			frame-number = <3>;

			frame-number = <3>;

			interrupts = <0 11 0x4>;

			interrupts = <0 11 0x4>;

			reg = <0xb025000 0x1000>;

			reg = <0xb125000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};





		frame@b026000 {

		frame@b126000 {

			frame-number = <4>;

			frame-number = <4>;

			interrupts = <0 12 0x4>;

			interrupts = <0 12 0x4>;

			reg = <0xb026000 0x1000>;

			reg = <0xb126000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};





		frame@b027000 {

		frame@b127000 {

			frame-number = <5>;

			frame-number = <5>;

			interrupts = <0 13 0x4>;

			interrupts = <0 13 0x4>;

			reg = <0xb027000 0x1000>;

			reg = <0xb127000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};





		frame@b028000 {

		frame@b128000 {

			frame-number = <6>;

			frame-number = <6>;

			interrupts = <0 14 0x4>;

			interrupts = <0 14 0x4>;

			reg = <0xb028000 0x1000>;

			reg = <0xb128000 0x1000>;

			status = "disabled";

			status = "disabled";

		};

		};

	};

	};