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Commit 4d30b283 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "defconfig: qcs405: Enable download and poweroff support in qcs405"

parents 74332269 bcc7933a

arch/arm/configs/vendor/qcs405_defconfig

+3 −0
Original line number Diff line number Diff line
@@ -275,6 +275,9 @@ CONFIG_SPMI_MSM_PMIC_ARB_DEBUG=y 
CONFIG_PINCTRL_QCS405=y

CONFIG_PINCTRL_QCOM_SPMI_PMIC=y

CONFIG_GPIOLIB=y

CONFIG_POWER_RESET=y

CONFIG_POWER_RESET_QCOM=y

CONFIG_QCOM_DLOAD_MODE=y

CONFIG_POWER_SUPPLY=y

CONFIG_SMB1351_USB_CHARGER=y

CONFIG_THERMAL=y

arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi

+22 −9
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
&soc {

	tlmm: pinctrl@1000000 {

		compatible = "qcom,qcs405-pinctrl";

		reg = <0x1000000 0x300000>;

		reg = <0x1000000 0x500000>;

		interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_NONE>;

		gpio-controller;

		#gpio-cells = <2>;
@@ -22,30 +22,43 @@ 
		interrupt-parent = <&wakegpio>;

		#interrupt-cells = <2>;



		pmx-uartconsole {

			uart_console_active: uart_console_active {

		blsp1_uart2_console {

			blsp_uart_tx_a2_active: blsp_uart_tx_a2_active {

				mux {

					pins = "gpio17", "gpio18";

					function = "blsp1_uart2";

					pins = "gpio17";

					function = "blsp_uart_tx_a2";

				};



				config {

					pins = "gpio17", "gpio18";

					pins = "gpio17";

					drive-strength = <2>;

					bias-disable;

				};

			};



			blsp_uart_rx_a2_active: blsp_uart_rx_a2_active {

				mux {

					pins = "gpio18";

					function = "blsp_uart_rx_a2";

				};



				config {

					pins = "gpio18";

					drive-strength = <2>;

					bias-disable;

				};

			};



			uart_console_sleep: uart_console_sleep {

			blsp_uart_tx_rx_a2_sleep: blsp_uart_tx_rx_a2_sleep {

				mux {

					pins = "gpio17", "gpio18";

					function = "blsp1_uart2";

					function = "gpio";

				};



				config {

					pins = "gpio17", "gpio18";

					drive-strength = <2>;

					bias-pull-down;

					bias-disable;

				};

			};

		};

arch/arm64/boot/dts/qcom/qcs405.dtsi

+8 −5
Original line number Diff line number Diff line
@@ -348,14 +348,17 @@ 
		status = "disabled";

	};



	blsp1_uart1: serial@78b0000 {

	blsp1_uart2_console: serial@78b1000 {

		compatible = "qcom,msm-uartdm", "qcom,msm-uartdm-v1.4";

		reg = <0x78b0000 0x200>;

		interrupts = <0 108 0>;



		clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,

		reg = <0x78b1000 0x200>;

		interrupts = <0 118 0>;

		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,

			<&clock_gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";

		pinctrl-names = "active", "sleep";

		pinctrl-0 = <&blsp_uart_tx_a2_active

			     &blsp_uart_rx_a2_active>;

		pinctrl-1 = <&blsp_uart_tx_rx_a2_sleep>;

		status = "okay";

	};

arch/arm64/configs/vendor/qcs405_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -279,6 +279,8 @@ CONFIG_SLIMBUS=y 
CONFIG_SLIMBUS_MSM_NGD=y

CONFIG_PINCTRL_QCS405=y

CONFIG_PINCTRL_QCOM_SPMI_PMIC=y

CONFIG_POWER_RESET_QCOM=y

CONFIG_QCOM_DLOAD_MODE=y

CONFIG_SMB1351_USB_CHARGER=y

CONFIG_THERMAL=y

CONFIG_THERMAL_WRITABLE_TRIPS=y