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Commit 4abe03d7 authored by Neeraj Soni's avatar Neeraj Soni Committed by Gerrit - the friendly Code Review server
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ARM: dts: Make crypto address part of host controller node 



New file encryption architecture parses crypto base address from
host controller node.

Change-Id: I73d67e82d11611c9d9f75da8fdc83ed10f1efeb2
Signed-off-by: default avatarNeeraj Soni <neersoni@codeaurora.org>
parent 162c3e7e

arch/arm64/boot/dts/qcom/atoll.dtsi

+4 −5
Original line number Diff line number Diff line
@@ -2679,13 +2679,12 @@ 


	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg-names = "hc_mem", "cmdq_mem";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;

		reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";



		interrupts = <GIC_SPI 641 IRQ_TYPE_NONE>,

					<GIC_SPI 644 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;
@@ -2835,11 +2834,11 @@ 


	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>;

		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+4 −5
Original line number Diff line number Diff line
@@ -2121,13 +2121,12 @@ 


	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg-names = "hc_mem", "cmdq_mem";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;

		reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";



		interrupts = <IRQ_TYPE_NONE 641 IRQ_TYPE_NONE>,

					<IRQ_TYPE_NONE 644 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;
@@ -2339,11 +2338,11 @@ 


	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>;

		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

arch/arm64/boot/dts/qcom/sm6150.dtsi

+4 −5
Original line number Diff line number Diff line
@@ -1409,12 +1409,11 @@ 


	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg-names = "hc_mem", "cmdq_mem";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;

		reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";



		interrupts = <0 641 0>, <0 644 0>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;
@@ -1623,11 +1622,11 @@ 


	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>;

		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

arch/arm64/boot/dts/qcom/sm8150.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -2281,7 +2281,6 @@ 
		reg = <0x1d87000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;
@@ -2297,11 +2296,11 @@ 


	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x2500>;

		reg = <0x1d84000 0x2500>, <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */