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Commit 4a928165 authored by Sudarshan Rajagopalan's avatar Sudarshan Rajagopalan
Browse files

iommu: arm-smmu: Add fault syndrome register-1 support 



The context bank Fault Syndrome Register 1, FSYNR1 is implementation
defined. Add support for printing the FSYNR1 info during context fault.
For targets that has this register unimplemented, the CPU read is RAZ.
This can be interpreted as 'unimplemented' with the known knowledge that
FSYNR1 is not implemented on the current target in use.

Change-Id: Icb831a074511365af64bd3ab635fed15c2e53224
Signed-off-by: default avatarSudarshan Rajagopalan <sudaraja@codeaurora.org>
parent f179ce65

drivers/iommu/arm-smmu-regs.h

+1 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ enum arm_smmu_s2cr_privcfg { 
#define ARM_SMMU_CB_FSRRESTORE		0x5c

#define ARM_SMMU_CB_FAR			0x60

#define ARM_SMMU_CB_FSYNR0		0x68

#define ARM_SMMU_CB_FSYNR1		0x6c

#define ARM_SMMU_CB_S1_TLBIVA		0x600

#define ARM_SMMU_CB_S1_TLBIASID		0x610

#define ARM_SMMU_CB_S1_TLBIALL		0x618

drivers/iommu/arm-smmu.c

+8 −8
Original line number Diff line number Diff line
@@ -1260,7 +1260,7 @@ static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain, 
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)

{

	int flags, ret, tmp;

	u32 fsr, fsynr, resume;

	u32 fsr, fsynr0, fsynr1, frsynra, resume;

	unsigned long iova;

	struct iommu_domain *domain = dev;

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
@@ -1270,7 +1270,6 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
	void __iomem *gr1_base;

	bool fatal_asf = smmu->options & ARM_SMMU_OPT_FATAL_ASF;

	phys_addr_t phys_soft;

	u32 frsynra;

	bool non_fatal_fault = !!(smmu_domain->attributes &

					(1 << DOMAIN_ATTR_NON_FATAL_FAULTS));
@@ -1297,8 +1296,9 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
		BUG();

	}



	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);

	flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;

	fsynr0 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);

	fsynr1 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR1);

	flags = fsynr0 & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;

	if (fsr & FSR_TF)

		flags |= IOMMU_FAULT_TRANSLATION;

	if (fsr & FSR_PF)
@@ -1315,8 +1315,8 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
	tmp = report_iommu_fault(domain, smmu->dev, iova, flags);

	if (!tmp || (tmp == -EBUSY)) {

		dev_dbg(smmu->dev,

			"Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",

			iova, fsr, fsynr, cfg->cbndx);

			"Context fault handled by client: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",

			iova, cfg->cbndx, fsr, fsynr0, fsynr1);

		dev_dbg(smmu->dev,

			"soft iova-to-phys=%pa\n", &phys_soft);

		ret = IRQ_HANDLED;
@@ -1326,8 +1326,8 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
							      fsr);

		if (__ratelimit(&_rs)) {

			dev_err(smmu->dev,

				"Unhandled context fault: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",

				iova, fsr, fsynr, cfg->cbndx);

				"Unhandled context fault: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",

				iova, cfg->cbndx, fsr, fsynr0, fsynr1);

			dev_err(smmu->dev, "FAR    = %016lx\n",

				(unsigned long)iova);

			dev_err(smmu->dev,