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Commit 4853cd4f authored by Gaurav Jindal's avatar Gaurav Jindal Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add svsl1 level for CSID clock in atoll 



Add the svs l1 clock level for CSID in atoll.

Change-Id: I9cffb4277599015d94b22682528687eda18be63e
Signed-off-by: default avatarGaurav Jindal <gjindal@codeaurora.org>
parent aff47579

arch/arm64/boot/dts/qcom/atoll-camera.dtsi

+6 −3
Original line number Diff line number Diff line
@@ -899,8 +899,9 @@ 
			<&clock_camcc CAM_CC_IFE_0_AXI_CLK>;

		clock-rates =

			<0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>,

			<0 0 0 0 0 0 360000000 0 0 0 432000000 0 0>,

			<0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>;

		clock-cntl-level = "svs", "turbo";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		ppi-enable;

		status = "ok";
@@ -987,8 +988,9 @@ 
			<&clock_camcc CAM_CC_IFE_1_AXI_CLK>;

		clock-rates =

			<0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>,

			<0 0 0 0 0 0 360000000 0 0 0 432000000 0 0>,

			<0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>;

		clock-cntl-level = "svs", "turbo";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		ppi-enable;

		status = "ok";
@@ -1072,8 +1074,9 @@ 
			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;

		clock-rates =

			<0 0 0 0 0 0 270000000 0 0 0 360000000 0>,

			<0 0 0 0 0 0 360000000 0 0 0 432000000 0>,

			<0 0 0 0 0 0 480000000 0 0 0 600000000 0>;

		clock-cntl-level = "svs", "turbo";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		ppi-enable;

		status = "ok";