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Commit 450174fe authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/chv: Tune L3 SQC credits based on actual latencies 



While browsing BSpec I bumped into a note saying we need to tune these
values based on actual measurements done after initial enabling. I've
checked that it indeed improves things on BXT. I haven't checked this on
CHV, but here it is if someone wants to give it a go.

v2:
- Add note about the discrepancy wrt. to the spec in the formula
  calculating the credit encodings. (Mika, Ville)
- Move the WA comment to the new function. (Ville)
v3:
- Keep the comment about the SQC WA in the caller. (Ville)

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
CC: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-4-git-send-email-imre.deak@intel.com
parent 36579cb6

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -6091,6 +6091,12 @@ enum skl_disp_power_wells { 
#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000



#define GEN8_L3SQCREG1				_MMIO(0xB100)

/*

 * Note that on CHV the following has an off-by-one error wrt. to BSpec.

 * Using the formula in BSpec leads to a hang, while the formula here works

 * fine and matches the formulas for all other platforms. A BSpec change

 * request has been filed to clarify this.

 */

#define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)

#define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)

drivers/gpu/drm/i915/intel_pm.c

+32 −16
Original line number Diff line number Diff line
@@ -6696,11 +6696,33 @@ static void lpt_suspend_hw(struct drm_device *dev) 
	}

}



static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,

				   int general_prio_credits,

				   int high_prio_credits)

{

	u32 misccpctl;



	/* WaTempDisableDOPClkGating:bdw */

	misccpctl = I915_READ(GEN7_MISCCPCTL);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);



	I915_WRITE(GEN8_L3SQCREG1,

		   L3_GENERAL_PRIO_CREDITS(general_prio_credits) |

		   L3_HIGH_PRIO_CREDITS(high_prio_credits));



	/*

	 * Wait at least 100 clocks before re-enabling clock gating.

	 * See the definition of L3SQCREG1 in BSpec.

	 */

	POSTING_READ(GEN8_L3SQCREG1);

	udelay(1);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

}



static void broadwell_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum pipe pipe;

	uint32_t misccpctl;



	ilk_init_lp_watermarks(dev);
@@ -6731,21 +6753,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/*

	 * WaProgramL3SqcReg1Default:bdw

	 * WaTempDisableDOPClkGating:bdw

	 */

	misccpctl = I915_READ(GEN7_MISCCPCTL);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(30) |

				   L3_HIGH_PRIO_CREDITS(2));

	/*

	 * Wait at least 100 clocks before re-enabling clock gating. See

	 * the definition of L3SQCREG1 in BSpec.

	 */

	POSTING_READ(GEN8_L3SQCREG1);

	udelay(1);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	/* WaProgramL3SqcReg1Default:bdw */

	gen8_set_l3sqc_credits(dev_priv, 30, 2);



	/*

	 * WaGttCachingOffByDefault:bdw
@@ -7015,6 +7024,13 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/*

	 * WaProgramL3SqcReg1Default:chv

	 * See gfxspecs/Related Documents/Performance Guide/

	 * LSQC Setting Recommendations.

	 */

	gen8_set_l3sqc_credits(dev_priv, 38, 2);



	/*

	 * GTT cache may not work with big pages, so if those

	 * are ever enabled GTT cache may need to be disabled.