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Commit 44e182bc authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: Avoid turning off the CPUSS AHB clocks during LPM state 



The clock driver sets the sleep_ena bits to allow the cpuss_ahb_clk
and sys_noc_cpuss_ahb_clk clocks to be disabled by hardware during
certain low power modes.
The PCIe hardware controller might however need these clocks to be
on at this time to make certain accesses, which then fail because
the clocks dont turn on automatically as expected.
Remove setting the sleep_ena bits to keep these clocks enabled at
all times, while the CX rail is on, in order to resolve this issue.

Change-Id: I2a5e69f6a405aa32bf9b36ab94e1dd228e514d6f
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent afa6ff3a

drivers/clk/qcom/gcc-sdm855.c

+1 −12
Original line number Diff line number Diff line
@@ -38,9 +38,6 @@ 


#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET	0x52008

#define CPUSS_AHB_CLK_SLEEP_ENA			BIT(21)

#define SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA		BIT(0)

#define GCC_NPU_MISC				0x4d110

#define GCC_GPU_MISC				0x71028
@@ -4460,15 +4457,7 @@ static int gcc_sdm855_probe(struct platform_device *pdev) 
	if (IS_ERR(regmap))

		return PTR_ERR(regmap);



	/*

	 * Set the *_SLEEP_ENA bits to allow certain cpuss* clocks to be

	 * turned off by hardware during certain apps low power modes.

	 */

	regmap_update_bits(regmap, GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET,

		CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA,

		CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA);



	/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */

	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */

	regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);

	regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);