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Commit 42fff322 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add inline crypto engine node for SM7150"

parents 74d45711 3ae00dab

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+47 −0
Original line number Original line Diff line number Diff line
@@ -1887,6 +1887,28 @@ 
		};

		};

	};

	};





	sdcc1_ice: sdcc1ice@7C8000 {

		compatible = "qcom,ice";

		reg = <0x7C8000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 757 0 0>,    /* No vote */

				<1 757 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@7c4000 {

	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5";

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
@@ -1895,6 +1917,7 @@ 
		interrupts = <IRQ_TYPE_NONE 641 IRQ_TYPE_NONE>,

		interrupts = <IRQ_TYPE_NONE 641 IRQ_TYPE_NONE>,

					<IRQ_TYPE_NONE 644 IRQ_TYPE_NONE>;

					<IRQ_TYPE_NONE 644 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;





		qcom,bus-width = <8>;

		qcom,bus-width = <8>;

		qcom,large-address-bus;

		qcom,large-address-bus;
@@ -1977,6 +2000,29 @@ 
		clock-names = "iface_clk";

		clock-names = "iface_clk";

	};

	};





	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xddc>; /* PHY regs */

		reg = <0x1d87000 0xddc>; /* PHY regs */

		reg-names = "phy_mem";

		reg-names = "phy_mem";
@@ -2000,6 +2046,7 @@ 
		interrupts = <0 265 0>;

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;





		lanes-per-direction = <1>;

		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		dev-ref-clk-freq = <0>; /* 19.2 MHz */