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Commit 42d485ca authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable GPIO function of GPIO171"

parents 4dccce1f d69ee6cf

arch/arm64/boot/dts/qcom/sa8155-vm-qupv3.dtsi

+23 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -317,6 +317,28 @@ 
		status = "disabled";

	};



	/* 4-wire UART */

	qupv3_se4_4uart: qcom,qup_uart@890000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x890000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S4_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,

				<&qupv3_se4_default_tx>;

		pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,

						<&qupv3_se4_tx>;

		pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,

						<&qupv3_se4_tx>;

		interrupts = <GIC_SPI 605 0>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};



	/* QUPv3 North & East Instances

	 * North 0 : SE 8

	 * North 1 : SE 9

arch/arm64/boot/dts/qcom/sa8195-vm-lv-lxc.dtsi

+4 −0
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@@ -38,6 +38,10 @@ 
	status = "ok";

};



&qupv3_se4_4uart {

	status = "ok";

};



&usb0 {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sa8195-vm.dtsi

+2 −0
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@@ -125,6 +125,8 @@ 


	aliases {

		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */

		hsuart0 = &qupv3_se13_4uart;

		hsuart1 = &qupv3_se4_4uart;

	};

};

arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi

+71 −2
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@@ -3743,12 +3743,12 @@ 


		bt_en_active: bt_en_active {

			mux {

				pins = "gpio172";

				pins = "gpio172", "gpio171";

				function = "gpio";

			};



			config {

				pins = "gpio172";

				pins = "gpio172", "gpio171";

				drive-strength = <2>;

				bias-pull-down;

			};
@@ -4059,6 +4059,75 @@ 
			};

		};



		qupv3_se4_4uart_pins: qupv3_se4_4uart_pins {

			qupv3_se4_default_ctsrtsrx:

				qupv3_se4_default_ctsrtsrx {

				mux {

					pins = "gpio51", "gpio52", "gpio54";

					function = "gpio";

				};



				config {

					pins = "gpio51", "gpio52", "gpio54";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se4_default_tx: qupv3_se4_default_tx {

				mux {

					pins = "gpio53";

					function = "gpio";

				};



				config {

					pins = "gpio53";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se4_ctsrx: qupv3_se4_ctsrx {

				mux {

					pins = "gpio51", "gpio54";

					function = "qup4";

				};



				config {

					pins = "gpio51", "gpio54";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se4_rts: qupv3_se4_rts {

				mux {

					pins = "gpio52";

					function = "qup4";

				};



				config {

					pins = "gpio52";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se4_tx: qupv3_se4_tx {

				mux {

					pins = "gpio53";

					function = "qup4";

				};



				config {

					pins = "gpio53";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



		};



		/* SE 5 pin mappings */

		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {

			qupv3_se5_i2c_active: qupv3_se5_i2c_active {

arch/arm64/boot/dts/qcom/sdmshrike-qupv3.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -327,6 +327,29 @@ 
		status = "disabled";

	};



	/* 4-wire UART */

	qupv3_se4_4uart: qcom,qup_uart@890000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x890000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,

				<&qupv3_se4_default_tx>;

		pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,

						<&qupv3_se4_tx>;

		pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,

						<&qupv3_se4_tx>;

		interrupts-extended = <&pdc GIC_SPI 605 0>,

				<&tlmm 54 0>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};



	/* QUPv3 East0 and East1 Instances

	 * East1 0 : SE 8

	 * East1 1 : SE 9