Merge "ARM: dts: msm: Add wcss tpdm for SM6150" (3fe40271) · Commits · e / devices / android_kernel_xiaomi_sm6125

arch/arm64/boot/dts/qcom/sm6150-coresight.dtsi

+95 −1

Original line number	Original line	Diff line number	Diff line
	@@ -442,6 +442,19 @@
	};		};
	};		};

			tpdm_wcss: tpdm@699c000 {
			compatible = "qcom,coresight-dummy";

			coresight-name = "coresight-tpdm-wcss";
			qcom,dummy-source;

			port {
			tpdm_wcss_out_funnel_in1: endpoint {
			remote-endpoint = <&funnel_in1_in_tpdm_wcss>;
			};
			};
			};

	tpdm_west: tpdm@6b48000 {		tpdm_west: tpdm@6b48000 {
	compatible = "arm,primecell";		compatible = "arm,primecell";
	arm,primecell-periphid = <0x0003b968>;		arm,primecell-periphid = <0x0003b968>;
	@@ -1017,6 +1030,15 @@
	};		};

	port@2 {		port@2 {
			reg = <4>;
			funnel_in1_in_tpdm_wcss: endpoint {
			slave-mode;
			remote-endpoint =
			<&tpdm_wcss_out_funnel_in1>;
			};
			};

			port@3 {
	reg = <7>;		reg = <7>;
	funnel_in1_in_funnel_apss_merg: endpoint {		funnel_in1_in_funnel_apss_merg: endpoint {
	slave-mode;		slave-mode;
	@@ -1356,6 +1378,78 @@
	};		};
	};		};

			cti0_dlct: cti@6c29000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6c29000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-dlct_cti0";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

			cti1_dlct: cti@6c2a000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6c2a000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-dlct_cti1";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

			cti0_ddr0: cti@6a02000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6a02000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-ddr_dl_0_cti0";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

			cti1_ddr0: cti@6a03000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6a03000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-ddr_dl_0_cti1";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

			cti0_ddr1: cti@6a10000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6a10000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-ddr_dl_1_cti0";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

			cti1_ddr1: cti@6a11000 {
			compatible = "arm,primecell";
			arm,primecell-periphid = <0x0003b966>;
			reg = <0x6a11000 0x1000>;
			reg-names = "cti-base";

			coresight-name = "coresight-cti-ddr_dl_1_cti1";

			clocks = <&clock_aop QDSS_CLK>;
			clock-names = "apb_pclk";
			};

	cti_mss_q6: cti@683b000 {		cti_mss_q6: cti@683b000 {
	compatible = "arm,primecell";		compatible = "arm,primecell";
	arm,primecell-periphid = <0x0003b966>;		arm,primecell-periphid = <0x0003b966>;