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Commit 3d65a735 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/mst: use max link not sink lane count 



The source might not support as many lanes as the sink, or the link
training might have failed at higher lane counts. Take these into
account.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/cf59530acafaf9258fb643d321ad251b44f34e29.1491485983.git.jani.nikula@intel.com
parent 540b0b7f

drivers/gpu/drm/i915/intel_dp.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -177,7 +177,7 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 
	return min(source_max, sink_max);

	return min(source_max, sink_max);

}

}





static int intel_dp_max_lane_count(struct intel_dp *intel_dp)

int intel_dp_max_lane_count(struct intel_dp *intel_dp)

{

{

	return intel_dp->max_link_lane_count;

	return intel_dp->max_link_lane_count;

}

}

drivers/gpu/drm/i915/intel_dp_mst.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -56,7 +56,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	 * for MST we always configure max link bw - the spec doesn't

	 * for MST we always configure max link bw - the spec doesn't

	 * seem to suggest we should do otherwise.

	 * seem to suggest we should do otherwise.

	 */

	 */

	lane_count = drm_dp_max_lane_count(intel_dp->dpcd);

	lane_count = intel_dp_max_lane_count(intel_dp);





	pipe_config->lane_count = lane_count;

	pipe_config->lane_count = lane_count;
@@ -343,7 +343,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, 
	int max_rate, mode_rate, max_lanes, max_link_clock;

	int max_rate, mode_rate, max_lanes, max_link_clock;





	max_link_clock = intel_dp_max_link_rate(intel_dp);

	max_link_clock = intel_dp_max_link_rate(intel_dp);

	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_lanes = intel_dp_max_lane_count(intel_dp);





	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);

	mode_rate = intel_dp_link_required(mode->clock, bpp);

	mode_rate = intel_dp_link_required(mode->clock, bpp);

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1503,6 +1503,7 @@ void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *co 
void intel_dp_mst_suspend(struct drm_device *dev);

void intel_dp_mst_suspend(struct drm_device *dev);

void intel_dp_mst_resume(struct drm_device *dev);

void intel_dp_mst_resume(struct drm_device *dev);

int intel_dp_max_link_rate(struct intel_dp *intel_dp);

int intel_dp_max_link_rate(struct intel_dp *intel_dp);

int intel_dp_max_lane_count(struct intel_dp *intel_dp);

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);

void intel_dp_hot_plug(struct intel_encoder *intel_encoder);

void intel_dp_hot_plug(struct intel_encoder *intel_encoder);

void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);

void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);