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Commit 3cd583d9 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: add toggle resync fifo on 7nm PHY 



Add resync fifo toggling for 7nm DSI phy programming
sequence.

Change-Id: I448d84608a24172731620f476d0f8dfa8d3ce107
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 2d23d0f2

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) 
		dsi_phy_hw_v4_0_is_lanes_in_ulps;

	phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;

	phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;

}



/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes); 
int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,

		u32 *timing_val, u32 size);

int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+10 −0
Original line number Diff line number Diff line
@@ -273,6 +273,16 @@ void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy, 
	pr_debug("[DSI_%d]Phy disabled ", phy->index);

}



void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy)

{

	DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);

	/* ensure that the FIFO is off */

	wmb();

	DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x1);

	/* ensure that the FIFO is toggled back on */

	wmb();

}



int dsi_phy_hw_v4_0_wait_for_lane_idle(

		struct dsi_phy_hw *phy, u32 lanes)

{