Loading Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt +1 −0 Original line number Diff line number Diff line Loading @@ -497,6 +497,7 @@ Optional properties: - qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel for any commands that we send. - qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression Loading drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c +267 −50 Original line number Diff line number Diff line Loading @@ -112,6 +112,7 @@ /* Register Offsets from PHY base address */ #define PHY_CMN_CLK_CFG0 0x010 #define PHY_CMN_CLK_CFG1 0x014 #define PHY_CMN_GLBL_CTRL 0x018 #define PHY_CMN_RBUF_CTRL 0x01c #define PHY_CMN_PLL_CNTRL 0x038 #define PHY_CMN_CTRL_0 0x024 Loading Loading @@ -209,6 +210,7 @@ struct dsi_pll_10nm { struct mdss_pll_resources *rsc; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; bool cphy_enabled; }; static inline int pll_reg_read(void *context, unsigned int reg, Loading Loading @@ -330,7 +332,7 @@ static inline int phy_reg_update_bits(void *context, unsigned int reg, return rc; } static inline int pclk_mux_read_sel(void *context, unsigned int reg, static int pclk_mux_read_sel(void *context, unsigned int reg, unsigned int *val) { int rc = 0; Loading Loading @@ -362,11 +364,12 @@ static inline int pclk_mux_write_sel_sub(struct mdss_pll_resources *rsc, return rc; } static inline int pclk_mux_write_sel(void *context, unsigned int reg, static int pclk_mux_write_sel(void *context, unsigned int reg, unsigned int val) { int rc = 0; struct mdss_pll_resources *rsc = context; struct dsi_pll_10nm *pll = rsc->priv; rc = mdss_pll_resource_enable(rsc, true); if (rc) { Loading @@ -374,6 +377,63 @@ static inline int pclk_mux_write_sel(void *context, unsigned int reg, return rc; } if (pll->cphy_enabled) WARN_ON("PHY is in CPHY mode. PLL config is incorrect\n"); rc = pclk_mux_write_sel_sub(rsc, reg, val); if (!rc && rsc->slave) rc = pclk_mux_write_sel_sub(rsc->slave, reg, val); (void)mdss_pll_resource_enable(rsc, false); /* * cache the current parent index for cases where parent * is not changing but rate is changing. In that case * clock framework won't call parent_set and hence dsiclk_sel * bit won't be programmed. e.g. dfps update use case. */ rsc->cached_cfg1 = val; return rc; } static int cphy_pclk_mux_read_sel(void *context, unsigned int reg, unsigned int *val) { int rc = 0; struct mdss_pll_resources *rsc = context; rc = mdss_pll_resource_enable(rsc, true); if (rc) { pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); return rc; } *val = (MDSS_PLL_REG_R(rsc->phy_base, reg) & 0x3); (void)mdss_pll_resource_enable(rsc, false); return rc; } static int cphy_pclk_mux_write_sel(void *context, unsigned int reg, unsigned int val) { int rc = 0; struct mdss_pll_resources *rsc = context; struct dsi_pll_10nm *pll = rsc->priv; rc = mdss_pll_resource_enable(rsc, true); if (rc) { pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); return rc; } if (!pll->cphy_enabled) WARN_ON("PHY-> not in CPHY mode. PLL config is incorrect\n"); /* For Cphy configuration, val should always be 3 */ val = 3; rc = pclk_mux_write_sel_sub(rsc, reg, val); if (!rc && rsc->slave) rc = pclk_mux_write_sel_sub(rsc->slave, reg, val); Loading Loading @@ -637,6 +697,14 @@ static void dsi_pll_init_val(struct mdss_pll_resources *rsc) MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x0); } static void dsi_pll_detect_phy_mode(struct dsi_pll_10nm *pll, struct mdss_pll_resources *rsc) { u32 reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_GLBL_CTRL); pll->cphy_enabled = (reg_val & BIT(6)) ? true : false; } static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct mdss_pll_resources *rsc) { Loading @@ -654,7 +722,8 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll, reg->frac_div_start_high); MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40); MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06); MDSS_PLL_REG_W(pll_base, PLL_CMODE, 0x10); MDSS_PLL_REG_W(pll_base, PLL_CMODE, pll->cphy_enabled ? 0x00 : 0x10); MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); } Loading Loading @@ -696,6 +765,8 @@ static int vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate, dsi_pll_init_val(rsc); dsi_pll_detect_phy_mode(pll, rsc); dsi_pll_setup_config(pll, rsc); dsi_pll_calc_dec_frac(pll, rsc); Loading Loading @@ -1004,11 +1075,19 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) { int rc; struct mdss_pll_resources *rsc = vco->priv; struct dsi_pll_10nm *pll = rsc->priv; dsi_pll_enable_pll_bias(rsc); if (rsc->slave) dsi_pll_enable_pll_bias(rsc->slave); /* For Cphy configuration, pclk_mux is always set to 3 divider */ if (pll->cphy_enabled) { rsc->cached_cfg1 |= 0x3; if (rsc->slave) rsc->slave->cached_cfg1 |= 0x3; } phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1); if (rsc->slave) phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1, Loading Loading @@ -1414,6 +1493,11 @@ static struct regmap_bus pclk_src_regmap_bus = { .reg_read = pixel_clk_get_div, }; static struct regmap_bus cphy_pclk_src_mux_regmap_bus = { .reg_read = cphy_pclk_mux_read_sel, .reg_write = cphy_pclk_mux_write_sel, }; static struct regmap_bus bitclk_src_regmap_bus = { .reg_write = bit_clk_set_div, .reg_read = bit_clk_get_div, Loading Loading @@ -1452,42 +1536,41 @@ static struct regmap_bus mdss_mux_regmap_bus = { * | DIV(1,2,4,8) | * +-------+-------+ * | * +-----------------------------+--------+ * +-----------------------------+-------+---------------+ * | | | | * +-------v-------+ | | | * | bitclk_src | | | | * | DIV(1..15) | | | | * +-------+-------+ | | | * | | | | * +-------------v+---------+---------+ | | | * | | | | | | | * +-----v-----+ +-----v-----+ | +------v------+ | +-----v------+ +-----v------+ * |byteclk_src| |byteclk_src| | |post_bit_div | | |post_vco_div| |post_vco_div| * | DIV(8) | | DIV(7) | | | DIV (2) | | | DIV(4) | | DIV(3.5) | * +-----+-----+ +-----+-----+ | +------+------+ | +-----+------+ +------+-----+ * | | | | | | | *Shadow Path | CPHY Path | | | | +----v * + | | +------+ | | +---+ | * +---+ | +-----+ | | | | | * | | | +-v--v----v---v---+ +--------v--------+ * +---v--v--------v---+ \ pclk_src_mux / \ cphy_pclk_src / * \ byteclk_mux / \ / \ mux / * \ / +-----+-----+ +-----+-----+ * +------+------+ | Shadow Path | * | | + | * v +-----v------+ | +------v------+ * dsi_byte_clk | pclk_src | | |cphy_pclk_src| * | DIV(1..15) | | | DIV(1..15) | * +-----+------+ | +------+------+ * | | | * +-------v-------+ | | * | bitclk_src | | | * | DIV(1..15) | | | * +-------+-------+ | | * | | CPHY Path * | | | * +----------+---------+ | | * Shadow Path | | | | | * + +-------v-------+ | +------v------+ | +------v-------+ * | | byteclk_src | | |post_bit_div | | |post_vco_div | * | | DIV(8) | | |DIV (2) | | |DIV(4) | * | +-------+-------+ | +------+------+ | +------+-------+ * | | | | | | | * | | | +------+ | | * | | +-------------+ | | +----+ * | +--------+ | | | | * | | +-v--v-v---v------+ * +-v---------v----+ \ pclk_src_mux / * \ byteclk_mux / \ / * \ / +-----+-----+ * +----+-----+ | Shadow Path * | | + * v +-----v------+ | * dsi_byte_clk | pclk_src | | * | DIV(1..15) | | * +-----+------+ | * | | * | | * +--------+ | * | | * +---v----v----+ * +-------+ | +-------+ * | | | * +---v---v----v------+ * \ pclk_mux / * \ / * +---+---+ * | * +------+------+ * | * v * dsi_pclk Loading Loading @@ -1718,6 +1801,30 @@ static struct clk_fixed_factor dsi1pll_shadow_post_vco_div = { }, }; static struct clk_fixed_factor dsi0pll_post_vco_div3_5 = { .div = 7, .mult = 2, .hw.init = &(struct clk_init_data){ .name = "dsi0pll_post_vco_div3_5", .parent_names = (const char *[]){"dsi0pll_pll_out_div"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = { .div = 7, .mult = 2, .hw.init = &(struct clk_init_data){ .name = "dsi1pll_post_vco_div3_5", .parent_names = (const char *[]){"dsi1pll_pll_out_div"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi0pll_byteclk_src = { .div = 8, .mult = 1, Loading Loading @@ -1766,6 +1873,30 @@ static struct clk_fixed_factor dsi1pll_shadow_byteclk_src = { }, }; static struct clk_fixed_factor dsi0pll_cphy_byteclk_src = { .div = 7, .mult = 1, .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_byteclk_src", .parent_names = (const char *[]){"dsi0pll_bitclk_src"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = { .div = 7, .mult = 1, .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_byteclk_src", .parent_names = (const char *[]){"dsi1pll_bitclk_src"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi0pll_post_bit_div = { .div = 2, .mult = 1, Loading Loading @@ -1821,8 +1952,9 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi0pll_byteclk_src", "dsi0pll_shadow_byteclk_src"}, .num_parents = 2, "dsi0pll_shadow_byteclk_src", "dsi0pll_cphy_byteclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -1837,8 +1969,9 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi1pll_byteclk_src", "dsi1pll_shadow_byteclk_src"}, .num_parents = 2, "dsi1pll_shadow_byteclk_src", "dsi1pll_cphy_byteclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading Loading @@ -1883,6 +2016,22 @@ static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = { }, }; static struct clk_regmap_mux dsi0pll_cphy_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, .width = 2, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_pclk_src_mux", .parent_names = (const char *[]){"dsi0pll_post_vco_div3_5"}, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_mux_closest_ops, }, }, }; static struct clk_regmap_mux dsi1pll_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, Loading Loading @@ -1920,6 +2069,22 @@ static struct clk_regmap_mux dsi1pll_shadow_pclk_src_mux = { }, }; static struct clk_regmap_mux dsi1pll_cphy_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, .width = 2, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_pclk_src_mux", .parent_names = (const char *[]){"dsi1pll_post_vco_div3_5"}, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_mux_closest_ops, }, }, }; static struct clk_regmap_div dsi0pll_pclk_src = { .shift = 0, .width = 4, Loading Loading @@ -1950,6 +2115,21 @@ static struct clk_regmap_div dsi0pll_shadow_pclk_src = { }, }; static struct clk_regmap_div dsi0pll_cphy_pclk_src = { .shift = 0, .width = 4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_pclk_src", .parent_names = (const char *[]){ "dsi0pll_cphy_pclk_src_mux"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, }; static struct clk_regmap_div dsi1pll_pclk_src = { .shift = 0, .width = 4, Loading Loading @@ -1980,6 +2160,21 @@ static struct clk_regmap_div dsi1pll_shadow_pclk_src = { }, }; static struct clk_regmap_div dsi1pll_cphy_pclk_src = { .shift = 0, .width = 4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_pclk_src", .parent_names = (const char *[]){ "dsi1pll_cphy_pclk_src_mux"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, }; static struct clk_regmap_mux dsi0pll_pclk_mux = { .shift = 0, .width = 1, Loading @@ -1987,8 +2182,9 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_dsiclk", .parent_names = (const char *[]){"dsi0pll_pclk_src", "dsi0pll_shadow_pclk_src"}, .num_parents = 2, "dsi0pll_shadow_pclk_src", "dsi0pll_cphy_pclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -2003,8 +2199,9 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_dsiclk", .parent_names = (const char *[]){"dsi1pll_pclk_src", "dsi1pll_shadow_pclk_src"}, .num_parents = 2, "dsi1pll_shadow_pclk_src", "dsi1pll_cphy_pclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -2017,12 +2214,16 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { [PLL_OUT_DIV_0_CLK] = &dsi0pll_pll_out_div.clkr.hw, [BITCLK_SRC_0_CLK] = &dsi0pll_bitclk_src.clkr.hw, [BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw, [CPHY_BYTECLK_SRC_0_CLK] = &dsi0pll_cphy_byteclk_src.hw, [POST_BIT_DIV_0_CLK] = &dsi0pll_post_bit_div.hw, [POST_VCO_DIV_0_CLK] = &dsi0pll_post_vco_div.hw, [POST_VCO_DIV3_5_0_CLK] = &dsi0pll_post_vco_div3_5.hw, [BYTECLK_MUX_0_CLK] = &dsi0pll_byteclk_mux.clkr.hw, [PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw, [PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw, [PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw, [CPHY_PCLK_SRC_MUX_0_CLK] = &dsi0pll_cphy_pclk_src_mux.clkr.hw, [CPHY_PCLK_SRC_0_CLK] = &dsi0pll_cphy_pclk_src.clkr.hw, [SHADOW_VCO_CLK_0] = &dsi0pll_shadow_vco_clk.hw, [SHADOW_PLL_OUT_DIV_0_CLK] = &dsi0pll_shadow_pll_out_div.clkr.hw, [SHADOW_BITCLK_SRC_0_CLK] = &dsi0pll_shadow_bitclk_src.clkr.hw, Loading @@ -2035,12 +2236,16 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { [PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw, [BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw, [BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw, [CPHY_BYTECLK_SRC_1_CLK] = &dsi1pll_cphy_byteclk_src.hw, [POST_BIT_DIV_1_CLK] = &dsi1pll_post_bit_div.hw, [POST_VCO_DIV_1_CLK] = &dsi1pll_post_vco_div.hw, [POST_VCO_DIV3_5_1_CLK] = &dsi1pll_post_vco_div3_5.hw, [BYTECLK_MUX_1_CLK] = &dsi1pll_byteclk_mux.clkr.hw, [PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw, [PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw, [PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw, [CPHY_PCLK_SRC_MUX_1_CLK] = &dsi1pll_cphy_pclk_src_mux.clkr.hw, [CPHY_PCLK_SRC_1_CLK] = &dsi1pll_cphy_pclk_src.clkr.hw, [SHADOW_VCO_CLK_1] = &dsi1pll_shadow_vco_clk.hw, [SHADOW_PLL_OUT_DIV_1_CLK] = &dsi1pll_shadow_pll_out_div.clkr.hw, [SHADOW_BITCLK_SRC_1_CLK] = &dsi1pll_shadow_bitclk_src.clkr.hw, Loading Loading @@ -2106,6 +2311,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_pclk_src.clkr.regmap = rmap; dsi0pll_cphy_pclk_src.clkr.regmap = rmap; dsi0pll_shadow_pclk_src.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, Loading @@ -2117,6 +2323,11 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, dsi0pll_pclk_src_mux.clkr.regmap = rmap; dsi0pll_shadow_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &cphy_pclk_src_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_cphy_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_byteclk_mux.clkr.regmap = rmap; Loading Loading @@ -2153,6 +2364,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_pclk_src.clkr.regmap = rmap; dsi1pll_cphy_pclk_src.clkr.regmap = rmap; dsi1pll_shadow_pclk_src.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, Loading @@ -2164,6 +2376,11 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, dsi1pll_pclk_src_mux.clkr.regmap = rmap; dsi1pll_shadow_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &cphy_pclk_src_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_cphy_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_byteclk_mux.clkr.regmap = rmap; Loading drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c +273 −56 File changed.Preview size limit exceeded, changes collapsed. Show changes drivers/gpu/drm/msm/dsi-staging/dsi_clk.h +5 −1 Original line number Diff line number Diff line Loading @@ -117,11 +117,13 @@ struct dsi_link_lp_clk_info { /** * struct link_clk_freq - Clock frequency information for Link clocks * @byte_clk_rate: Frequency of DSI byte_clk in KHz. * @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in KHz. * @pixel_clk_rate: Frequency of DSI pixel_clk in KHz. * @esc_clk_rate: Frequency of DSI escape clock in KHz. */ struct link_clk_freq { u32 byte_clk_rate; u32 byte_intf_clk_rate; u32 pix_clk_rate; u32 esc_clk_rate; }; Loading Loading @@ -306,10 +308,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); * dsi_clk_set_byte_clk_rate() - set frequency for byte clock * @client: DSI clock client pointer. * @byte_clk: Pixel clock rate in Hz. * @byte_intf_clk: Byte interface clock rate in Hz. * @index: Index of the DSI controller. * return: error code in case of failure or 0 for success. */ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index); int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u64 byte_intf_clk, u32 index); /** * dsi_clk_update_parent() - update parent clocks for specified clock Loading drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c +8 −7 Original line number Diff line number Diff line Loading @@ -139,15 +139,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) * dsi_clk_set_byte_clk_rate() - set frequency for byte clock * @client: DSI clock client pointer. * @byte_clk: Byte clock rate in Hz. * @byte_intf_clk: Byte interface clock rate in Hz. * @index: Index of the DSI controller. * return: error code in case of failure or 0 for success. */ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u64 byte_intf_clk, u32 index) { int rc = 0; struct dsi_clk_client_info *c = client; struct dsi_clk_mngr *mngr; u64 byte_intf_rate; mngr = c->mngr; rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk); Loading @@ -157,12 +158,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) mngr->link_clks[index].freq.byte_clk_rate = byte_clk; if (mngr->link_clks[index].hs_clks.byte_intf_clk) { byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2; rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk, byte_intf_rate); byte_intf_clk); if (rc) pr_err("failed to set clk rate for byte intf clk=%d\n", rc); else mngr->link_clks[index].freq.byte_intf_clk_rate = byte_intf_clk; } return rc; Loading Loading @@ -371,12 +374,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks, /* * If byte_intf_clk is present, set rate for that too. * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2 * todo: this needs to be revisited when support for CPHY is added */ if (link_hs_clks->byte_intf_clk) { rc = clk_set_rate(link_hs_clks->byte_intf_clk, (l_clks->freq.byte_clk_rate / 2)); l_clks->freq.byte_intf_clk_rate); if (rc) { pr_err("set_rate failed for byte_intf_clk rc = %d\n", rc); Loading Loading
Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt +1 −0 Original line number Diff line number Diff line Loading @@ -497,6 +497,7 @@ Optional properties: - qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel for any commands that we send. - qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c +267 −50 Original line number Diff line number Diff line Loading @@ -112,6 +112,7 @@ /* Register Offsets from PHY base address */ #define PHY_CMN_CLK_CFG0 0x010 #define PHY_CMN_CLK_CFG1 0x014 #define PHY_CMN_GLBL_CTRL 0x018 #define PHY_CMN_RBUF_CTRL 0x01c #define PHY_CMN_PLL_CNTRL 0x038 #define PHY_CMN_CTRL_0 0x024 Loading Loading @@ -209,6 +210,7 @@ struct dsi_pll_10nm { struct mdss_pll_resources *rsc; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; bool cphy_enabled; }; static inline int pll_reg_read(void *context, unsigned int reg, Loading Loading @@ -330,7 +332,7 @@ static inline int phy_reg_update_bits(void *context, unsigned int reg, return rc; } static inline int pclk_mux_read_sel(void *context, unsigned int reg, static int pclk_mux_read_sel(void *context, unsigned int reg, unsigned int *val) { int rc = 0; Loading Loading @@ -362,11 +364,12 @@ static inline int pclk_mux_write_sel_sub(struct mdss_pll_resources *rsc, return rc; } static inline int pclk_mux_write_sel(void *context, unsigned int reg, static int pclk_mux_write_sel(void *context, unsigned int reg, unsigned int val) { int rc = 0; struct mdss_pll_resources *rsc = context; struct dsi_pll_10nm *pll = rsc->priv; rc = mdss_pll_resource_enable(rsc, true); if (rc) { Loading @@ -374,6 +377,63 @@ static inline int pclk_mux_write_sel(void *context, unsigned int reg, return rc; } if (pll->cphy_enabled) WARN_ON("PHY is in CPHY mode. PLL config is incorrect\n"); rc = pclk_mux_write_sel_sub(rsc, reg, val); if (!rc && rsc->slave) rc = pclk_mux_write_sel_sub(rsc->slave, reg, val); (void)mdss_pll_resource_enable(rsc, false); /* * cache the current parent index for cases where parent * is not changing but rate is changing. In that case * clock framework won't call parent_set and hence dsiclk_sel * bit won't be programmed. e.g. dfps update use case. */ rsc->cached_cfg1 = val; return rc; } static int cphy_pclk_mux_read_sel(void *context, unsigned int reg, unsigned int *val) { int rc = 0; struct mdss_pll_resources *rsc = context; rc = mdss_pll_resource_enable(rsc, true); if (rc) { pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); return rc; } *val = (MDSS_PLL_REG_R(rsc->phy_base, reg) & 0x3); (void)mdss_pll_resource_enable(rsc, false); return rc; } static int cphy_pclk_mux_write_sel(void *context, unsigned int reg, unsigned int val) { int rc = 0; struct mdss_pll_resources *rsc = context; struct dsi_pll_10nm *pll = rsc->priv; rc = mdss_pll_resource_enable(rsc, true); if (rc) { pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); return rc; } if (!pll->cphy_enabled) WARN_ON("PHY-> not in CPHY mode. PLL config is incorrect\n"); /* For Cphy configuration, val should always be 3 */ val = 3; rc = pclk_mux_write_sel_sub(rsc, reg, val); if (!rc && rsc->slave) rc = pclk_mux_write_sel_sub(rsc->slave, reg, val); Loading Loading @@ -637,6 +697,14 @@ static void dsi_pll_init_val(struct mdss_pll_resources *rsc) MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x0); } static void dsi_pll_detect_phy_mode(struct dsi_pll_10nm *pll, struct mdss_pll_resources *rsc) { u32 reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_GLBL_CTRL); pll->cphy_enabled = (reg_val & BIT(6)) ? true : false; } static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct mdss_pll_resources *rsc) { Loading @@ -654,7 +722,8 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll, reg->frac_div_start_high); MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40); MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06); MDSS_PLL_REG_W(pll_base, PLL_CMODE, 0x10); MDSS_PLL_REG_W(pll_base, PLL_CMODE, pll->cphy_enabled ? 0x00 : 0x10); MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); } Loading Loading @@ -696,6 +765,8 @@ static int vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate, dsi_pll_init_val(rsc); dsi_pll_detect_phy_mode(pll, rsc); dsi_pll_setup_config(pll, rsc); dsi_pll_calc_dec_frac(pll, rsc); Loading Loading @@ -1004,11 +1075,19 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) { int rc; struct mdss_pll_resources *rsc = vco->priv; struct dsi_pll_10nm *pll = rsc->priv; dsi_pll_enable_pll_bias(rsc); if (rsc->slave) dsi_pll_enable_pll_bias(rsc->slave); /* For Cphy configuration, pclk_mux is always set to 3 divider */ if (pll->cphy_enabled) { rsc->cached_cfg1 |= 0x3; if (rsc->slave) rsc->slave->cached_cfg1 |= 0x3; } phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1); if (rsc->slave) phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1, Loading Loading @@ -1414,6 +1493,11 @@ static struct regmap_bus pclk_src_regmap_bus = { .reg_read = pixel_clk_get_div, }; static struct regmap_bus cphy_pclk_src_mux_regmap_bus = { .reg_read = cphy_pclk_mux_read_sel, .reg_write = cphy_pclk_mux_write_sel, }; static struct regmap_bus bitclk_src_regmap_bus = { .reg_write = bit_clk_set_div, .reg_read = bit_clk_get_div, Loading Loading @@ -1452,42 +1536,41 @@ static struct regmap_bus mdss_mux_regmap_bus = { * | DIV(1,2,4,8) | * +-------+-------+ * | * +-----------------------------+--------+ * +-----------------------------+-------+---------------+ * | | | | * +-------v-------+ | | | * | bitclk_src | | | | * | DIV(1..15) | | | | * +-------+-------+ | | | * | | | | * +-------------v+---------+---------+ | | | * | | | | | | | * +-----v-----+ +-----v-----+ | +------v------+ | +-----v------+ +-----v------+ * |byteclk_src| |byteclk_src| | |post_bit_div | | |post_vco_div| |post_vco_div| * | DIV(8) | | DIV(7) | | | DIV (2) | | | DIV(4) | | DIV(3.5) | * +-----+-----+ +-----+-----+ | +------+------+ | +-----+------+ +------+-----+ * | | | | | | | *Shadow Path | CPHY Path | | | | +----v * + | | +------+ | | +---+ | * +---+ | +-----+ | | | | | * | | | +-v--v----v---v---+ +--------v--------+ * +---v--v--------v---+ \ pclk_src_mux / \ cphy_pclk_src / * \ byteclk_mux / \ / \ mux / * \ / +-----+-----+ +-----+-----+ * +------+------+ | Shadow Path | * | | + | * v +-----v------+ | +------v------+ * dsi_byte_clk | pclk_src | | |cphy_pclk_src| * | DIV(1..15) | | | DIV(1..15) | * +-----+------+ | +------+------+ * | | | * +-------v-------+ | | * | bitclk_src | | | * | DIV(1..15) | | | * +-------+-------+ | | * | | CPHY Path * | | | * +----------+---------+ | | * Shadow Path | | | | | * + +-------v-------+ | +------v------+ | +------v-------+ * | | byteclk_src | | |post_bit_div | | |post_vco_div | * | | DIV(8) | | |DIV (2) | | |DIV(4) | * | +-------+-------+ | +------+------+ | +------+-------+ * | | | | | | | * | | | +------+ | | * | | +-------------+ | | +----+ * | +--------+ | | | | * | | +-v--v-v---v------+ * +-v---------v----+ \ pclk_src_mux / * \ byteclk_mux / \ / * \ / +-----+-----+ * +----+-----+ | Shadow Path * | | + * v +-----v------+ | * dsi_byte_clk | pclk_src | | * | DIV(1..15) | | * +-----+------+ | * | | * | | * +--------+ | * | | * +---v----v----+ * +-------+ | +-------+ * | | | * +---v---v----v------+ * \ pclk_mux / * \ / * +---+---+ * | * +------+------+ * | * v * dsi_pclk Loading Loading @@ -1718,6 +1801,30 @@ static struct clk_fixed_factor dsi1pll_shadow_post_vco_div = { }, }; static struct clk_fixed_factor dsi0pll_post_vco_div3_5 = { .div = 7, .mult = 2, .hw.init = &(struct clk_init_data){ .name = "dsi0pll_post_vco_div3_5", .parent_names = (const char *[]){"dsi0pll_pll_out_div"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = { .div = 7, .mult = 2, .hw.init = &(struct clk_init_data){ .name = "dsi1pll_post_vco_div3_5", .parent_names = (const char *[]){"dsi1pll_pll_out_div"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi0pll_byteclk_src = { .div = 8, .mult = 1, Loading Loading @@ -1766,6 +1873,30 @@ static struct clk_fixed_factor dsi1pll_shadow_byteclk_src = { }, }; static struct clk_fixed_factor dsi0pll_cphy_byteclk_src = { .div = 7, .mult = 1, .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_byteclk_src", .parent_names = (const char *[]){"dsi0pll_bitclk_src"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = { .div = 7, .mult = 1, .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_byteclk_src", .parent_names = (const char *[]){"dsi1pll_bitclk_src"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; static struct clk_fixed_factor dsi0pll_post_bit_div = { .div = 2, .mult = 1, Loading Loading @@ -1821,8 +1952,9 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi0pll_byteclk_src", "dsi0pll_shadow_byteclk_src"}, .num_parents = 2, "dsi0pll_shadow_byteclk_src", "dsi0pll_cphy_byteclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -1837,8 +1969,9 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi1pll_byteclk_src", "dsi1pll_shadow_byteclk_src"}, .num_parents = 2, "dsi1pll_shadow_byteclk_src", "dsi1pll_cphy_byteclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading Loading @@ -1883,6 +2016,22 @@ static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = { }, }; static struct clk_regmap_mux dsi0pll_cphy_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, .width = 2, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_pclk_src_mux", .parent_names = (const char *[]){"dsi0pll_post_vco_div3_5"}, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_mux_closest_ops, }, }, }; static struct clk_regmap_mux dsi1pll_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, Loading Loading @@ -1920,6 +2069,22 @@ static struct clk_regmap_mux dsi1pll_shadow_pclk_src_mux = { }, }; static struct clk_regmap_mux dsi1pll_cphy_pclk_src_mux = { .reg = PHY_CMN_CLK_CFG1, .shift = 0, .width = 2, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_pclk_src_mux", .parent_names = (const char *[]){"dsi1pll_post_vco_div3_5"}, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_mux_closest_ops, }, }, }; static struct clk_regmap_div dsi0pll_pclk_src = { .shift = 0, .width = 4, Loading Loading @@ -1950,6 +2115,21 @@ static struct clk_regmap_div dsi0pll_shadow_pclk_src = { }, }; static struct clk_regmap_div dsi0pll_cphy_pclk_src = { .shift = 0, .width = 4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0pll_cphy_pclk_src", .parent_names = (const char *[]){ "dsi0pll_cphy_pclk_src_mux"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, }; static struct clk_regmap_div dsi1pll_pclk_src = { .shift = 0, .width = 4, Loading Loading @@ -1980,6 +2160,21 @@ static struct clk_regmap_div dsi1pll_shadow_pclk_src = { }, }; static struct clk_regmap_div dsi1pll_cphy_pclk_src = { .shift = 0, .width = 4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1pll_cphy_pclk_src", .parent_names = (const char *[]){ "dsi1pll_cphy_pclk_src_mux"}, .num_parents = 1, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, }; static struct clk_regmap_mux dsi0pll_pclk_mux = { .shift = 0, .width = 1, Loading @@ -1987,8 +2182,9 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_dsiclk", .parent_names = (const char *[]){"dsi0pll_pclk_src", "dsi0pll_shadow_pclk_src"}, .num_parents = 2, "dsi0pll_shadow_pclk_src", "dsi0pll_cphy_pclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -2003,8 +2199,9 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_dsiclk", .parent_names = (const char *[]){"dsi1pll_pclk_src", "dsi1pll_shadow_pclk_src"}, .num_parents = 2, "dsi1pll_shadow_pclk_src", "dsi1pll_cphy_pclk_src"}, .num_parents = 3, .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), .ops = &clk_regmap_mux_closest_ops, Loading @@ -2017,12 +2214,16 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { [PLL_OUT_DIV_0_CLK] = &dsi0pll_pll_out_div.clkr.hw, [BITCLK_SRC_0_CLK] = &dsi0pll_bitclk_src.clkr.hw, [BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw, [CPHY_BYTECLK_SRC_0_CLK] = &dsi0pll_cphy_byteclk_src.hw, [POST_BIT_DIV_0_CLK] = &dsi0pll_post_bit_div.hw, [POST_VCO_DIV_0_CLK] = &dsi0pll_post_vco_div.hw, [POST_VCO_DIV3_5_0_CLK] = &dsi0pll_post_vco_div3_5.hw, [BYTECLK_MUX_0_CLK] = &dsi0pll_byteclk_mux.clkr.hw, [PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw, [PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw, [PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw, [CPHY_PCLK_SRC_MUX_0_CLK] = &dsi0pll_cphy_pclk_src_mux.clkr.hw, [CPHY_PCLK_SRC_0_CLK] = &dsi0pll_cphy_pclk_src.clkr.hw, [SHADOW_VCO_CLK_0] = &dsi0pll_shadow_vco_clk.hw, [SHADOW_PLL_OUT_DIV_0_CLK] = &dsi0pll_shadow_pll_out_div.clkr.hw, [SHADOW_BITCLK_SRC_0_CLK] = &dsi0pll_shadow_bitclk_src.clkr.hw, Loading @@ -2035,12 +2236,16 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { [PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw, [BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw, [BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw, [CPHY_BYTECLK_SRC_1_CLK] = &dsi1pll_cphy_byteclk_src.hw, [POST_BIT_DIV_1_CLK] = &dsi1pll_post_bit_div.hw, [POST_VCO_DIV_1_CLK] = &dsi1pll_post_vco_div.hw, [POST_VCO_DIV3_5_1_CLK] = &dsi1pll_post_vco_div3_5.hw, [BYTECLK_MUX_1_CLK] = &dsi1pll_byteclk_mux.clkr.hw, [PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw, [PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw, [PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw, [CPHY_PCLK_SRC_MUX_1_CLK] = &dsi1pll_cphy_pclk_src_mux.clkr.hw, [CPHY_PCLK_SRC_1_CLK] = &dsi1pll_cphy_pclk_src.clkr.hw, [SHADOW_VCO_CLK_1] = &dsi1pll_shadow_vco_clk.hw, [SHADOW_PLL_OUT_DIV_1_CLK] = &dsi1pll_shadow_pll_out_div.clkr.hw, [SHADOW_BITCLK_SRC_1_CLK] = &dsi1pll_shadow_bitclk_src.clkr.hw, Loading Loading @@ -2106,6 +2311,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_pclk_src.clkr.regmap = rmap; dsi0pll_cphy_pclk_src.clkr.regmap = rmap; dsi0pll_shadow_pclk_src.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, Loading @@ -2117,6 +2323,11 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, dsi0pll_pclk_src_mux.clkr.regmap = rmap; dsi0pll_shadow_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &cphy_pclk_src_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_cphy_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi0pll_byteclk_mux.clkr.regmap = rmap; Loading Loading @@ -2153,6 +2364,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_pclk_src.clkr.regmap = rmap; dsi1pll_cphy_pclk_src.clkr.regmap = rmap; dsi1pll_shadow_pclk_src.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, Loading @@ -2164,6 +2376,11 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, dsi1pll_pclk_src_mux.clkr.regmap = rmap; dsi1pll_shadow_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &cphy_pclk_src_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_cphy_pclk_src_mux.clkr.regmap = rmap; rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus, pll_res, &dsi_pll_10nm_config); dsi1pll_byteclk_mux.clkr.regmap = rmap; Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c +273 −56 File changed.Preview size limit exceeded, changes collapsed. Show changes
drivers/gpu/drm/msm/dsi-staging/dsi_clk.h +5 −1 Original line number Diff line number Diff line Loading @@ -117,11 +117,13 @@ struct dsi_link_lp_clk_info { /** * struct link_clk_freq - Clock frequency information for Link clocks * @byte_clk_rate: Frequency of DSI byte_clk in KHz. * @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in KHz. * @pixel_clk_rate: Frequency of DSI pixel_clk in KHz. * @esc_clk_rate: Frequency of DSI escape clock in KHz. */ struct link_clk_freq { u32 byte_clk_rate; u32 byte_intf_clk_rate; u32 pix_clk_rate; u32 esc_clk_rate; }; Loading Loading @@ -306,10 +308,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); * dsi_clk_set_byte_clk_rate() - set frequency for byte clock * @client: DSI clock client pointer. * @byte_clk: Pixel clock rate in Hz. * @byte_intf_clk: Byte interface clock rate in Hz. * @index: Index of the DSI controller. * return: error code in case of failure or 0 for success. */ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index); int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u64 byte_intf_clk, u32 index); /** * dsi_clk_update_parent() - update parent clocks for specified clock Loading
drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c +8 −7 Original line number Diff line number Diff line Loading @@ -139,15 +139,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) * dsi_clk_set_byte_clk_rate() - set frequency for byte clock * @client: DSI clock client pointer. * @byte_clk: Byte clock rate in Hz. * @byte_intf_clk: Byte interface clock rate in Hz. * @index: Index of the DSI controller. * return: error code in case of failure or 0 for success. */ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u64 byte_intf_clk, u32 index) { int rc = 0; struct dsi_clk_client_info *c = client; struct dsi_clk_mngr *mngr; u64 byte_intf_rate; mngr = c->mngr; rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk); Loading @@ -157,12 +158,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) mngr->link_clks[index].freq.byte_clk_rate = byte_clk; if (mngr->link_clks[index].hs_clks.byte_intf_clk) { byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2; rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk, byte_intf_rate); byte_intf_clk); if (rc) pr_err("failed to set clk rate for byte intf clk=%d\n", rc); else mngr->link_clks[index].freq.byte_intf_clk_rate = byte_intf_clk; } return rc; Loading Loading @@ -371,12 +374,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks, /* * If byte_intf_clk is present, set rate for that too. * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2 * todo: this needs to be revisited when support for CPHY is added */ if (link_hs_clks->byte_intf_clk) { rc = clk_set_rate(link_hs_clks->byte_intf_clk, (l_clks->freq.byte_clk_rate / 2)); l_clks->freq.byte_intf_clk_rate); if (rc) { pr_err("set_rate failed for byte_intf_clk rc = %d\n", rc); Loading
