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Commit 37a5a1e6 authored by Jilai Wang's avatar Jilai Wang
Browse files

Revert "ARM: dts: Update NPU clocks for sm8150" 



This reverts commit a849d364.

Change-Id: I1594ac81f1143f190c24d35caa7a9c70a2ead3ce
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent d36974bb

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+144 −144
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;

		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,

				<&clock_npucc NPU_CC_XO_CLK>,

				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,
@@ -34,15 +35,15 @@ 
				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,

				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

					<&clock_npucc NPU_CC_SLEEP_CLK>,

					<&clock_gcc GCC_NPU_AT_CLK>,

					<&clock_gcc GCC_NPU_TRIG_CLK>;

				<&clock_npucc NPU_CC_SLEEP_CLK>;

		clock-names = "cal_dp_clk",

				"cal_dp_clk_src",

				"xo_clk",

				"armwic_core_clk",

				"bto_core_clk",
@@ -53,14 +54,13 @@ 
				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"npu_core_clk",

				"npu_core_clk_src",

				"npu_core_cti_clk",

				"npu_cpc_clk",

				"npu_cpc_timer_clk",

				"perf_cnt_clk",

				"qtimer_core_clk",

						"sleep_clk",

						"at_clk",

						"trig_clk";

				"sleep_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";
@@ -77,6 +77,7 @@ 
			qcom,npu-pwrlevel@0 {

				reg = <0>;

				clk-freq = <9600000

						9600000

						19200000

						19200000

						19200000
@@ -90,15 +91,15 @@ 
						19200000

						19200000

						19200000

						19200000

						9600000

						19200000

							0

							0

						0>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				clk-freq = <300000000

						300000000

						19200000

						100000000

						19200000
@@ -109,18 +110,18 @@ 
						19200000

						60000000

						100000000

						100000000

						37500000

						100000000

						19200000

						300000000

						19200000

							0

							0

						0>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				clk-freq = <350000000

						350000000

						19200000

						150000000

						19200000
@@ -131,18 +132,18 @@ 
						19200000

						120000000

						150000000

						150000000

						75000000

						150000000

						19200000

						350000000

						19200000

							0

							0

						0>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				clk-freq = <400000000

						400000000

						19200000

						200000000

						19200000
@@ -153,18 +154,18 @@ 
						19200000

						120000000

						200000000

						200000000

						75000000

						200000000

						19200000

						400000000

						19200000

							0

							0

						0>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				clk-freq = <600000000

						600000000

						19200000

						300000000

						19200000
@@ -175,18 +176,18 @@ 
						19200000

						240000000

						300000000

						300000000

						150000000

						300000000

						19200000

						600000000

						19200000

							0

							0

						0>;

			};

			qcom,npu-pwrlevel@5 {

				reg = <5>;

				clk-freq = <715000000

						715000000

						19200000

						350000000

						19200000
@@ -197,13 +198,12 @@ 
						19200000

						240000000

						350000000

						350000000

						150000000

						350000000

						19200000

						715000000

						19200000

							0

							0

						0>;

			};

		};