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Commit 36f50a5c authored by David Woodhouse's avatar David Woodhouse Committed by Greg Kroah-Hartman
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tools headers: Synchronise x86 cpufeatures.h for L1TF additions 



commit e24f14b0ff985f3e09e573ba1134bfdf42987e05 upstream

Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 06f412c6

tools/arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ 
#define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */

#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
@@ -338,6 +339,7 @@ 
#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

#define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
@@ -370,5 +372,6 @@ 
#define X86_BUG_SPECTRE_V1		X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */

#define X86_BUG_SPECTRE_V2		X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */

#define X86_BUG_SPEC_STORE_BYPASS	X86_BUG(17) /* CPU is affected by speculative store bypass attack */

#define X86_BUG_L1TF			X86_BUG(18) /* CPU is affected by L1 Terminal Fault */



#endif /* _ASM_X86_CPUFEATURES_H */