Loading arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -835,6 +835,8 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_gfx-supply = <&VDD_GFX_LEVEL>; vdd_gfx-supply = <&VDD_GFX_LEVEL>; qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; #clock-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; #reset-cells = <1>; }; }; Loading Loading
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +2 −0 Original line number Original line Diff line number Diff line Loading @@ -835,6 +835,8 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_gfx-supply = <&VDD_GFX_LEVEL>; vdd_gfx-supply = <&VDD_GFX_LEVEL>; qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; #clock-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; #reset-cells = <1>; }; }; Loading