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Commit 2ff61bd6 authored by Ramandeep Trehan's avatar Ramandeep Trehan
Browse files

ARM: dts: msm: add inline crypto engine node for trinket 



Add inline crypto engine device node to support hardware encryption.

Change-Id: I4c3ccd95f60aa6284ad53e3051a0a24656afba48
Signed-off-by: default avatarRamandeep Trehan <rtrehan@codeaurora.org>
parent 30af045f

arch/arm64/boot/dts/qcom/trinket.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -1763,6 +1763,28 @@ 
		};

	};



	sdcc1_ice: sdcc1ice@4748000{

		compatible = "qcom,ice";

		reg = <0x4748000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 757 0 0>,    /* No vote */

				<1 757 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@4744000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x4744000 0x1000>, <0x4745000 0x1000>;
@@ -1771,6 +1793,7 @@ 
		interrupts = <GIC_SPI 348 IRQ_TYPE_NONE>,

					<GIC_SPI 352 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;