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Commit 2ea871ff authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: Add scc plls as fixed clocks for sm6150/sm8150 



Add SCC PLLs as fixed clock because LPASS has ownership over
it and they are always enabled and running at fixed frequency.

Change-Id: I6c59b3398f652ebe4b4f48b5a25c9cd927c494d5
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent d97648e5

arch/arm64/boot/dts/qcom/sm6150.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -803,6 +803,22 @@ 
			clock-output-names = "chip_sleep_clk";

			#clock-cells = <1>;

		};



		scc_pll_out_aux2: scc_pll_out_aux2 {

			compatible = "fixed-clock";

			clock-frequency = <600000000>;

			clock-output-names = "scc_pll_out_aux2";

			#clock-cells = <0>;

		};



		scc_pll_out_aux: scc_pll_out_aux {

			compatible = "fixed-factor-clock";

			clock-output-names = "scc_pll_out_aux";

			clocks = <&scc_pll_out_aux2>;

			clock-mult = <1>;

			clock-div = <2>;

			#clock-cells = <0>;

		};

	};



	clock_rpmh: qcom,rpmhclk {

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+5 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -86,6 +86,10 @@ 
	compatible = "qcom,npucc-sm8150-v2", "syscon";

};



&scc_pll {

	clock-frequency = <576000000>;

};



&clock_scc {

	compatible = "qcom,scc-sm8150-v2";

};

arch/arm64/boot/dts/qcom/sm8150.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -1017,6 +1017,24 @@ 
		};

	};



	clocks {

		scc_pll: scc_pll {

			compatible = "fixed-clock";

			clock-frequency = <600000000>;

			clock-output-names = "scc_pll";

			#clock-cells = <0>;

		};



		scc_pll_out_even: scc_pll_out_even {

			compatible = "fixed-factor-clock";

			clock-output-names = "scc_pll_out_even";

			clocks = <&scc_pll>;

			clock-mult = <1>;

			clock-div = <2>;

			#clock-cells = <0>;

		};

	};



	llcc_pmu: llcc-pmu@90cc000 {

		compatible = "qcom,qcom-llcc-pmu";

		reg = <0x090cc000 0x300>;