Loading Documentation/admin-guide/hw-vuln/mds.rst +5 −2 Original line number Diff line number Diff line Loading @@ -265,8 +265,11 @@ time with the option "mds=". The valid arguments for this option are: ============ ============================================================= Not specifying this option is equivalent to "mds=full". Not specifying this option is equivalent to "mds=full". For processors that are affected by both TAA (TSX Asynchronous Abort) and MDS, specifying just "mds=off" without an accompanying "tsx_async_abort=off" will have no effect as the same mitigation is used for both vulnerabilities. Mitigation selection guide -------------------------- Loading Documentation/admin-guide/hw-vuln/tsx_async_abort.rst +4 −1 Original line number Diff line number Diff line Loading @@ -174,7 +174,10 @@ the option "tsx_async_abort=". The valid arguments for this option are: CPU is not vulnerable to cross-thread TAA attacks. ============ ============================================================= Not specifying this option is equivalent to "tsx_async_abort=full". Not specifying this option is equivalent to "tsx_async_abort=full". For processors that are affected by both TAA and MDS, specifying just "tsx_async_abort=off" without an accompanying "mds=off" will have no effect as the same mitigation is used for both vulnerabilities. The kernel command line also allows to control the TSX feature using the parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used Loading Documentation/admin-guide/kernel-parameters.txt +11 −0 Original line number Diff line number Diff line Loading @@ -2276,6 +2276,12 @@ SMT on vulnerable CPUs off - Unconditionally disable MDS mitigation On TAA-affected machines, mds=off can be prevented by an active TAA mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify tsx_async_abort=off too. Not specifying this option is equivalent to mds=full. Loading Loading @@ -4625,6 +4631,11 @@ vulnerable to cross-thread TAA attacks. off - Unconditionally disable TAA mitigation On MDS-affected machines, tsx_async_abort=off can be prevented by an active MDS mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify mds=off too. Not specifying this option is equivalent to tsx_async_abort=full. On CPUs which are MDS affected and deploy MDS mitigation, TAA mitigation is not Loading Documentation/devicetree/bindings/arm/coresight.txt +10 −0 Original line number Diff line number Diff line Loading @@ -100,6 +100,16 @@ its hardware characteristcs. * Optional properties for all components: * reg-names: names corresponding to each reg property value. * Optional properties for all components: * arm,coresight-loses-context-with-cpu : boolean. Indicates that the hardware will lose register context on CPU power down (e.g. CPUIdle). An example of where this may be needed are systems which contain a coresight component and CPU in the same power domain. When the CPU powers down the coresight component also powers down and loses its context. This property is currently only used for the ETM 4.x driver. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management Loading Documentation/hid/uhid.txt +1 −1 Original line number Diff line number Diff line Loading @@ -160,7 +160,7 @@ them but you should handle them according to your needs. UHID_OUTPUT: This is sent if the HID device driver wants to send raw data to the I/O device on the interrupt channel. You should read the payload and forward it to the device. The payload is of type "struct uhid_data_req". the device. The payload is of type "struct uhid_output_req". This may be received even though you haven't received UHID_OPEN, yet. UHID_GET_REPORT: Loading Loading
Documentation/admin-guide/hw-vuln/mds.rst +5 −2 Original line number Diff line number Diff line Loading @@ -265,8 +265,11 @@ time with the option "mds=". The valid arguments for this option are: ============ ============================================================= Not specifying this option is equivalent to "mds=full". Not specifying this option is equivalent to "mds=full". For processors that are affected by both TAA (TSX Asynchronous Abort) and MDS, specifying just "mds=off" without an accompanying "tsx_async_abort=off" will have no effect as the same mitigation is used for both vulnerabilities. Mitigation selection guide -------------------------- Loading
Documentation/admin-guide/hw-vuln/tsx_async_abort.rst +4 −1 Original line number Diff line number Diff line Loading @@ -174,7 +174,10 @@ the option "tsx_async_abort=". The valid arguments for this option are: CPU is not vulnerable to cross-thread TAA attacks. ============ ============================================================= Not specifying this option is equivalent to "tsx_async_abort=full". Not specifying this option is equivalent to "tsx_async_abort=full". For processors that are affected by both TAA and MDS, specifying just "tsx_async_abort=off" without an accompanying "mds=off" will have no effect as the same mitigation is used for both vulnerabilities. The kernel command line also allows to control the TSX feature using the parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used Loading
Documentation/admin-guide/kernel-parameters.txt +11 −0 Original line number Diff line number Diff line Loading @@ -2276,6 +2276,12 @@ SMT on vulnerable CPUs off - Unconditionally disable MDS mitigation On TAA-affected machines, mds=off can be prevented by an active TAA mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify tsx_async_abort=off too. Not specifying this option is equivalent to mds=full. Loading Loading @@ -4625,6 +4631,11 @@ vulnerable to cross-thread TAA attacks. off - Unconditionally disable TAA mitigation On MDS-affected machines, tsx_async_abort=off can be prevented by an active MDS mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify mds=off too. Not specifying this option is equivalent to tsx_async_abort=full. On CPUs which are MDS affected and deploy MDS mitigation, TAA mitigation is not Loading
Documentation/devicetree/bindings/arm/coresight.txt +10 −0 Original line number Diff line number Diff line Loading @@ -100,6 +100,16 @@ its hardware characteristcs. * Optional properties for all components: * reg-names: names corresponding to each reg property value. * Optional properties for all components: * arm,coresight-loses-context-with-cpu : boolean. Indicates that the hardware will lose register context on CPU power down (e.g. CPUIdle). An example of where this may be needed are systems which contain a coresight component and CPU in the same power domain. When the CPU powers down the coresight component also powers down and loses its context. This property is currently only used for the ETM 4.x driver. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management Loading
Documentation/hid/uhid.txt +1 −1 Original line number Diff line number Diff line Loading @@ -160,7 +160,7 @@ them but you should handle them according to your needs. UHID_OUTPUT: This is sent if the HID device driver wants to send raw data to the I/O device on the interrupt channel. You should read the payload and forward it to the device. The payload is of type "struct uhid_data_req". the device. The payload is of type "struct uhid_output_req". This may be received even though you haven't received UHID_OPEN, yet. UHID_GET_REPORT: Loading