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Commit 2a3ca889 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14.c4"

parents 25147a8e 173bdf17

Documentation/devicetree/bindings/display/msm/sde.txt

+2 −0
Original line number Diff line number Diff line
@@ -446,6 +446,8 @@ Optional properties: 
				1: priority have to be explicitly configured for a given pair of pipes.

- qcom,sde-num-mnoc-ports:	A u32 property to indicate the number of mnoc ports

- qcom,sde-axi-bus-width:	A u32 property to indicate the axi bus width value in bytes

- qcom,sde-mixer-stage-base-layer: A boolean property to indicate if a layer can be staged on base

				stage instead of border fill



Bus Scaling Subnodes:

- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for

arch/arm64/boot/dts/qcom/trinket-sde.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 


		qcom,sde-mixer-cwb-pref = "none", "cwb", "none",

					      "none", "none", "none";

		qcom,sde-mixer-stage-base-layer;



		qcom,sde-dspp-top-off = <0x1300>;

		qcom,sde-dspp-top-size = <0x80>;
@@ -127,7 +128,7 @@ 
		qcom,sde-mixer-linewidth = <2560>;

		qcom,sde-sspp-linewidth = <2160>;

		qcom,sde-wb-linewidth = <2160>;

		qcom,sde-mixer-blendstages = <0x5>;

		qcom,sde-mixer-blendstages = <0x6>;

		qcom,sde-highest-bank-bit = <0x1>;

		qcom,sde-ubwc-version = <0x100>;

		qcom,sde-ubwc-swizzle = <1>;

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+5 −45
Original line number Diff line number Diff line
@@ -1212,13 +1212,6 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, 
	struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);

	struct mdss_pll_resources *pll = vco->priv;

	int rc;

	u64 ref_clk = vco->ref_clk_rate;

	u64 vco_rate;

	u64 multiplier;

	u32 frac;

	u32 dec;

	u32 outdiv;

	u64 pll_freq, tmp64;



	if (!vco->priv)

		pr_err("vco priv is null\n");
@@ -1229,12 +1222,10 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, 
	}



	/*

	 * Calculate the vco rate from HW registers only for handoff cases.

	 * For other cases where a vco_10nm_set_rate() has already been

	 * called, just return the rate that was set earlier. This is due

	 * to the fact that recalculating VCO rate requires us to read the

	 * correct value of the pll_out_div divider clock, which is only set

	 * afterwards.

	 * In the case when vco arte is set, the recalculation function should

	 * return the current rate as to avoid trying to set the vco rate

	 * again. However durng handoff, recalculation should set the flag

	 * according to the status of PLL.

	 */

	if (pll->vco_current_rate != 0) {

		pr_debug("returning vco rate = %lld\n", pll->vco_current_rate);
@@ -1251,40 +1242,9 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, 
	if (!dsi_pll_10nm_lock_status(pll))

		pll->handoff_resources = true;



	dec = MDSS_PLL_REG_R(pll->pll_base, PLL_DECIMAL_DIV_START_1);

	dec &= 0xFF;



	frac = MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_LOW_1);

	frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_MID_1) &

		  0xFF) <<

		8);

	frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_HIGH_1) &

		  0x3) <<

		16);



	/* OUTDIV_1:0 field is (log(outdiv, 2)) */

	outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_PLL_OUTDIV_RATE);

	outdiv &= 0x3;

	outdiv = 1 << outdiv;



	/*

	 * TODO:

	 *	1. Assumes prescaler is disabled

	 *	2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)

	 **/

	multiplier = 1 << 18;

	pll_freq = dec * (ref_clk * 2);

	tmp64 = (ref_clk * 2 * frac);

	pll_freq += div_u64(tmp64, multiplier);



	vco_rate = div_u64(pll_freq, outdiv);



	pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n",

		 dec, frac, outdiv, vco_rate);



	(void)mdss_pll_resource_enable(pll, false);



	return (unsigned long)vco_rate;

	return rc;

}



static int pixel_clk_get_div(void *context, unsigned int reg, unsigned int *div)

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+6 −48
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1146,13 +1146,6 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, 
	struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);

	struct mdss_pll_resources *pll = vco->priv;

	int rc;

	u64 ref_clk = vco->ref_clk_rate;

	u64 vco_rate = 0;

	u64 multiplier;

	u32 frac;

	u32 dec;

	u32 outdiv;

	u64 pll_freq, tmp64;



	if (!vco->priv) {

		pr_err("vco priv is null\n");
@@ -1160,12 +1153,10 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, 
	}



	/*

	 * Calculate the vco rate from HW registers only for handoff cases.

	 * For other cases where a vco_10nm_set_rate() has already been

	 * called, just return the rate that was set earlier. This is due

	 * to the fact that recalculating VCO rate requires us to read the

	 * correct value of the pll_out_div divider clock, which is only set

	 * afterwards.

	 * In the case when vco arte is set, the recalculation function should

	 * return the current rate as to avoid trying to set the vco rate

	 * again. However durng handoff, recalculation should set the flag

	 * according to the status of PLL.

	 */

	if (pll->vco_current_rate != 0) {

		pr_debug("returning vco rate = %lld\n", pll->vco_current_rate);
@@ -1183,43 +1174,10 @@ static unsigned long vco_7nm_recalc_rate(struct clk_hw *hw, 
	if (dsi_pll_7nm_lock_status(pll)) {

		pr_debug("PLL not enabled\n");

		pll->handoff_resources = false;

		goto end;

	}



	dec = MDSS_PLL_REG_R(pll->pll_base, PLL_DECIMAL_DIV_START_1);

	dec &= 0xFF;



	frac = MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_LOW_1);

	frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_MID_1) &

		  0xFF) <<

		8);

	frac |= ((MDSS_PLL_REG_R(pll->pll_base, PLL_FRAC_DIV_START_HIGH_1) &

		  0x3) <<

		16);



	/* OUTDIV_1:0 field is (log(outdiv, 2)) */

	outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_PLL_OUTDIV_RATE);

	outdiv &= 0x3;

	outdiv = 1 << outdiv;



	/*

	 * TODO:

	 *	1. Assumes prescaler is disabled

	 *	2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)

	 **/

	multiplier = 1 << 18;

	pll_freq = dec * (ref_clk * 2);

	tmp64 = (ref_clk * 2 * frac);

	pll_freq += div_u64(tmp64, multiplier);



	vco_rate = div_u64(pll_freq, outdiv);



	pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n",

		 dec, frac, outdiv, vco_rate);



end:

	(void)mdss_pll_resource_enable(pll, false);

	return (unsigned long)vco_rate;

	return rc;

}



static int pixel_clk_get_div(void *context, unsigned int reg, unsigned int *div)

drivers/gpu/drm/msm/sde/sde_core_perf.c

+1 −28
Original line number Diff line number Diff line
@@ -84,28 +84,6 @@ static bool _sde_core_perf_crtc_is_power_on(struct drm_crtc *crtc) 
	return sde_crtc_is_enabled(crtc);

}



static bool _sde_core_video_mode_intf_connected(struct drm_crtc *crtc)

{

	struct drm_crtc *tmp_crtc;

	bool intf_connected = false;



	if (!crtc)

		goto end;



	drm_for_each_crtc(tmp_crtc, crtc->dev) {

		if ((sde_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) &&

				_sde_core_perf_crtc_is_power_on(tmp_crtc)) {

			SDE_DEBUG("video interface connected crtc:%d\n",

				tmp_crtc->base.id);

			intf_connected = true;

			goto end;

		}

	}



end:

	return intf_connected;

}



static void _sde_core_perf_calc_crtc(struct sde_kms *kms,

		struct drm_crtc *crtc,

		struct drm_crtc_state *state,
@@ -198,7 +176,6 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc, 
	u32 bw, threshold;

	u64 bw_sum_of_intfs = 0;

	enum sde_crtc_client_type curr_client_type;

	bool is_video_mode;

	struct sde_crtc_state *sde_cstate;

	struct drm_crtc *tmp_crtc;

	struct sde_kms *kms;
@@ -251,11 +228,7 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc, 
		bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);

		SDE_DEBUG("calculated bandwidth=%uk\n", bw);



		is_video_mode = sde_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO;

		threshold = (is_video_mode ||

			_sde_core_video_mode_intf_connected(crtc)) ?

			kms->catalog->perf.max_bw_low :

			kms->catalog->perf.max_bw_high;

		threshold = kms->catalog->perf.max_bw_high;



		SDE_DEBUG("final threshold bw limit = %d\n", threshold);