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Commit 28d8e093 authored by Oleg Perelet's avatar Oleg Perelet
Browse files

msm: kgsl: enable hardware clockgating on A6XX GPU 



Program all hardware clockgating registers are per hw spec.

Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
Change-Id: I50b20ddba86b8eb99cc9e426f133b21319661c4d
parent cb57e6b4

drivers/gpu/msm/a6xx_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -519,6 +519,9 @@ 
#define A6XX_RBBM_CLOCK_DELAY_HLSQ_2	 0x00117

#define A6XX_RBBM_CLOCK_CNTL_GMU_GX      0x00118

#define A6XX_RBBM_CLOCK_DELAY_GMU_GX     0x00119

#define A6XX_RBBM_CLOCK_CNTL_TEX_FCHE    0x00120

#define A6XX_RBBM_CLOCK_DELAY_TEX_FCHE   0x00121

#define A6XX_RBBM_CLOCK_HYST_TEX_FCHE    0x00122

#define A6XX_RBBM_CLOCK_HYST_GMU_GX      0x0011a

#define A6XX_RBBM_CLOCK_MODE_HLSQ	 0x0011b

#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c

drivers/gpu/msm/adreno_a6xx.c

+27 −80
Original line number Diff line number Diff line
@@ -253,110 +253,49 @@ static const struct kgsl_hwcg_reg a615_hwcg_regs[] = { 
};



static const struct kgsl_hwcg_reg a640_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},

	{A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x00000081},

	{A6XX_RBBM_CLOCK_HYST_SP1, 0x00000081},

	{A6XX_RBBM_CLOCK_HYST_SP2, 0x00000081},

	{A6XX_RBBM_CLOCK_HYST_SP3, 0x00000081},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},

	{A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},

	{A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},

	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},

	{A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},

	{A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},

	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},

	{A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},

	{A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},

	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL2_RB1, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL2_RB2, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL2_RB3, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},

	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL, 0xAAA8AA82},

	{A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},

	{A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},

	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_ISDB_CNT, 0x00000182},

	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
@@ -628,6 +567,8 @@ __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a615(adreno_dev))

		return 0x8AA8AA82;

	else if (adreno_is_a640(adreno_dev))

		return 0x8AA8AA82;

	else

		return 0x8AA8AA02;

}
@@ -637,6 +578,8 @@ __get_gmu_ao_cgc_mode_cntl(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a615(adreno_dev))

		return 0x00000222;

	else if (adreno_is_a640(adreno_dev))

		return 0x00020202;

	else

		return 0x00020202;

}
@@ -646,6 +589,8 @@ __get_gmu_ao_cgc_delay_cntl(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a615(adreno_dev))

		return 0x00000111;

	else if (adreno_is_a640(adreno_dev))

		return 0x00010111;

	else

		return 0x00010111;

}
@@ -655,6 +600,8 @@ __get_gmu_ao_cgc_hyst_cntl(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a615(adreno_dev))

		return 0x00000555;

	else if (adreno_is_a640(adreno_dev))

		return 0x00005555;

	else

		return 0x00005555;

}