Merge changes Iebf83135,I818d6f17 into msm-next (1fcc36f0) · Commits · e / devices / android_kernel_xiaomi_sm6125

drivers/clk/clk.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -648,7 +648,7 @@ static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
		/*
		* Vote for a voltage level corresponding to a clock's rate.
		*/
		static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
		int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
		{
		int level;

		@@ -661,11 +661,12 @@ static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)

		return clk_vote_vdd_level(core->vdd_class, level);
		}
		EXPORT_SYMBOL_GPL(clk_vote_rate_vdd);

		/*
		* Remove vote for a voltage level corresponding to a clock's rate.
		*/
		static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
		void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
		{
		int level;

		@@ -678,6 +679,7 @@ static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)

		clk_unvote_vdd_level(core->vdd_class, level);
		}
		EXPORT_SYMBOL_GPL(clk_unvote_rate_vdd);

		static bool clk_is_rate_level_valid(struct clk_core *core, unsigned long rate)
		{

drivers/clk/qcom/clk-alpha-pll.c

+439 −9

Original line number	Diff line number	Diff line
		@@ -61,6 +61,31 @@
		#define ALPHA_REG_BITWIDTH 40
		#define ALPHA_BITWIDTH 32
		#define ALPHA_16BIT_MASK 0xffff
		#define TRION_PLL_BITWIDTH 16

		/* TRION PLL specific settings and offsets */
		#define TRION_PLL_CAL_L_VAL 0x8
		#define TRION_PLL_USER_CTL 0xc
		#define TRION_PLL_USER_CTL_U 0x10
		#define TRION_PLL_USER_CTL_U1 0x14
		#define TRION_PLL_CONFIG_CTL 0x18
		#define TRION_PLL_CONFIG_CTL_U 0x1c
		#define TRION_PLL_CONFIG_CTL_U1 0x20
		#define TRION_PLL_OPMODE 0x38
		#define TRION_PLL_ALPHA_VAL 0x40
		#define TRION_PLL_STATUS 0x30

		#define TRION_PLL_CAL_VAL 0x44
		#define TRION_PLL_STANDBY 0x0
		#define TRION_PLL_RUN 0x1
		#define TRION_PLL_OUT_MASK 0x7
		#define TRION_PCAL_DONE BIT(26)
		#define TRION_PLL_RATE_MARGIN 500
		#define TRION_PLL_ACK_LATCH BIT(29)
		#define TRION_PLL_UPDATE BIT(22)
		#define TRION_PLL_HW_UPDATE_LOGIC_BYPASS BIT(23)

		#define XO_RATE 19200000

		#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
		struct clk_alpha_pll, clkr)
		@@ -306,16 +331,33 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
		regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
		}

		static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
		static unsigned long alpha_pll_calc_rate(const struct clk_alpha_pll *pll,
		u64 prate, u32 l, u32 a)
		{
		return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
		int alpha_bw = ALPHA_BITWIDTH;

		if (pll->type == TRION_PLL)
		alpha_bw = TRION_PLL_BITWIDTH;

		return (prate * l) + ((prate * a) >> alpha_bw);
		}

		static unsigned long
		alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 l, u64 a)
		alpha_pll_round_rate(const struct clk_alpha_pll *pll, unsigned long rate,
		unsigned long prate, u32 l, u64 a)
		{
		u64 remainder;
		u64 quotient;
		int alpha_bw = ALPHA_BITWIDTH;

		/*
		* The PLLs parent rate is zero probably since the parent hasn't
		* registered yet. Return early with the requested rate.
		*/
		if (!prate) {
		pr_warn("PLLs parent rate hasn't been initialized.\n");
		return rate;
		}

		quotient = rate;
		remainder = do_div(quotient, prate);
		@@ -326,15 +368,19 @@ alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 l, u64 a)
		return rate;
		}

		/* Trion PLLs only have 16 bits to program the fractional divider */
		if (pll->type == TRION_PLL)
		alpha_bw = TRION_PLL_BITWIDTH;

		/* Upper ALPHA_BITWIDTH bits of Alpha */
		quotient = remainder << ALPHA_BITWIDTH;
		quotient = remainder << alpha_bw;
		remainder = do_div(quotient, prate);

		if (remainder)
		quotient++;

		*a = quotient;
		return alpha_pll_calc_rate(prate, l, a);
		return alpha_pll_calc_rate(pll, prate, l, a);
		}

		static const struct pll_vco *
		@@ -373,7 +419,7 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		}
		}

		return alpha_pll_calc_rate(prate, l, a);
		return alpha_pll_calc_rate(pll, prate, l, a);
		}

		static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		@@ -384,7 +430,7 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		u32 l, off = pll->offset;
		u64 a;

		rate = alpha_pll_round_rate(rate, prate, &l, &a);
		rate = alpha_pll_round_rate(pll, rate, prate, &l, &a);
		vco = alpha_pll_find_vco(pll, rate);
		if (!vco) {
		pr_err("alpha pll not in a valid vco range\n");
		@@ -419,8 +465,8 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
		u64 a;
		unsigned long min_freq, max_freq;

		rate = alpha_pll_round_rate(rate, *prate, &l, &a);
		if (alpha_pll_find_vco(pll, rate))
		rate = alpha_pll_round_rate(pll, rate, *prate, &l, &a);
		if (pll->type != TRION_PLL && alpha_pll_find_vco(pll, rate))
		return rate;

		min_freq = pll->vco_table[0].min_freq;
		@@ -464,6 +510,289 @@ static void clk_alpha_pll_list_registers(struct seq_file f, struct clk_hw hw)
		}
		}

		static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
		struct regmap *regmap)
		{
		u32 mode_regval, opmode_regval;
		int ret;

		ret = regmap_read(regmap, pll->offset + PLL_MODE, &mode_regval);
		ret \|= regmap_read(regmap, pll->offset + TRION_PLL_OPMODE,
		&opmode_regval);
		if (ret)
		return 0;

		return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
		}

		int clk_trion_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config)
		{
		int ret = 0;

		if (trion_pll_is_enabled(pll, regmap)) {
		pr_warn("PLL is already enabled. Skipping configuration.\n");
		return ret;
		}

		/*
		* Disable the PLL if it's already been initialized. Not doing so might
		* lead to the PLL running with the old frequency configuration.
		*/
		if (pll->inited) {
		ret = regmap_update_bits(regmap, pll->offset + PLL_MODE,
		PLL_RESET_N, 0);
		if (ret)
		return ret;
		}

		if (config->l)
		regmap_write(regmap, pll->offset + PLL_L_VAL,
		config->l);

		regmap_write(regmap, pll->offset + TRION_PLL_CAL_L_VAL,
		TRION_PLL_CAL_VAL);

		if (config->alpha)
		regmap_write(regmap, pll->offset + TRION_PLL_ALPHA_VAL,
		config->alpha);
		if (config->config_ctl_val)
		regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL,
		config->config_ctl_val);

		if (config->config_ctl_hi_val)
		regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U,
		config->config_ctl_hi_val);

		if (config->config_ctl_hi1_val)
		regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U1,
		config->config_ctl_hi1_val);

		if (config->post_div_mask)
		regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL,
		config->post_div_mask, config->post_div_val);

		regmap_update_bits(regmap, pll->offset + PLL_MODE,
		TRION_PLL_HW_UPDATE_LOGIC_BYPASS,
		TRION_PLL_HW_UPDATE_LOGIC_BYPASS);

		/* Disable PLL output */
		ret = regmap_update_bits(regmap, pll->offset + PLL_MODE,
		PLL_OUTCTRL, 0);
		if (ret)
		return ret;

		/* Set operation mode to OFF */
		regmap_write(regmap, pll->offset + TRION_PLL_OPMODE,
		TRION_PLL_STANDBY);

		/* PLL should be in OFF mode before continuing */
		wmb();

		/* Place the PLL in STANDBY mode */
		ret = regmap_update_bits(regmap, pll->offset + PLL_MODE,
		PLL_RESET_N, PLL_RESET_N);
		if (ret)
		return ret;

		pll->inited = true;
		return 0;
		}

		static int clk_trion_pll_enable(struct clk_hw *hw)
		{
		int ret;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val, off = pll->offset;

		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
		if (ret)
		return ret;

		/* If in FSM mode, just vote for it */
		if (val & PLL_VOTE_FSM_ENA) {
		ret = clk_enable_regmap(hw);
		if (ret)
		return ret;
		return wait_for_pll_enable_active(pll);
		}

		if (unlikely(!pll->inited)) {
		ret = clk_trion_pll_configure(pll, pll->clkr.regmap,
		pll->config);
		if (ret) {
		pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
		return ret;
		}
		}

		/* Set operation mode to RUN */
		regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE, TRION_PLL_RUN);

		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;

		/* Enable the PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL,
		TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
		if (ret)
		return ret;

		/* Enable the global PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
		PLL_OUTCTRL, PLL_OUTCTRL);
		if (ret)
		return ret;

		/* Ensure that the write above goes through before returning. */
		mb();
		return ret;
		}

		static void clk_trion_pll_disable(struct clk_hw *hw)
		{
		int ret;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val, off = pll->offset;

		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
		if (ret)
		return;

		/* If in FSM mode, just unvote it */
		if (val & PLL_VOTE_FSM_ENA) {
		clk_disable_regmap(hw);
		return;
		}

		/* Disable the global PLL output */
		ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
		PLL_OUTCTRL, 0);
		if (ret)
		return;

		/* Disable the PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL,
		TRION_PLL_OUT_MASK, 0);
		if (ret)
		return;

		/* Place the PLL mode in STANDBY */
		regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE,
		TRION_PLL_STANDBY);

		regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_RESET_N,
		PLL_RESET_N);
		}

		/*
		* The Trion PLL requires a power-on self-calibration which happens when the
		* PLL comes out of reset. The calibration is performed at an output frequency
		* of ~1300 MHz which means that SW will have to vote on a voltage that's
		* equal to or greater than SVS_L1 on the corresponding rail. Since this is not
		* feasable to do in the atomic enable path, temporarily bring up the PLL here,
		* let it calibrate, and place it in standby before returning.
		*/
		static int clk_trion_pll_prepare(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 regval;
		int ret = 0;

		/* Return early if calibration is not needed. */
		regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_STATUS, &regval);
		if (regval & TRION_PCAL_DONE)
		return ret;

		ret = clk_vote_rate_vdd(hw->core, TRION_PLL_CAL_VAL * XO_RATE);
		if (ret)
		return ret;

		ret = clk_trion_pll_enable(hw);
		if (ret)
		goto ret_path;

		clk_trion_pll_disable(hw);
		ret_path:
		clk_unvote_rate_vdd(hw->core, TRION_PLL_CAL_VAL * XO_RATE);
		return ret;
		}

		static unsigned long
		clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		{
		u32 l, frac;
		u64 prate = parent_rate;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 off = pll->offset;

		regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
		regmap_read(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, &frac);

		return alpha_pll_calc_rate(pll, prate, l, frac);
		}

		static int clk_trion_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long prate)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		unsigned long rrate;
		u32 regval, l, off = pll->offset;
		u64 a;
		int ret;

		rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a);
		/*
		* Due to a limited number of bits for fractional rate programming, the
		* rounded up rate could be marginally higher than the requested rate.
		*/
		if (rrate > (rate + TRION_PLL_RATE_MARGIN) \|\| rrate < rate) {
		pr_err("Call set rate on the PLL with rounded rates!\n");
		return -EINVAL;
		}

		regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
		regmap_write(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, a);

		/* Latch the PLL input */
		ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
		TRION_PLL_UPDATE, TRION_PLL_UPDATE);
		if (ret)
		return ret;

		/* Wait for 2 reference cycles before checking the ACK bit. */
		udelay(1);
		regmap_read(pll->clkr.regmap, off + PLL_MODE, &regval);
		if (!(regval & TRION_PLL_ACK_LATCH)) {
		WARN(1, "PLL latch failed. Output may be unstable!\n");
		return -EINVAL;
		}

		/* Return the latch input to 0 */
		ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
		TRION_PLL_UPDATE, 0);
		if (ret)
		return ret;

		if (clk_hw_is_enabled(hw)) {
		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;
		}

		/* Wait for PLL output to stabilize */
		udelay(100);
		return 0;
		}

		static int clk_trion_pll_is_enabled(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

		return trion_pll_is_enabled(pll, pll->clkr.regmap);
		}

		const struct clk_ops clk_alpha_pll_ops = {
		.enable = clk_alpha_pll_enable,
		.disable = clk_alpha_pll_disable,
		@@ -486,6 +815,26 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);

		const struct clk_ops clk_trion_pll_ops = {
		.prepare = clk_trion_pll_prepare,
		.enable = clk_trion_pll_enable,
		.disable = clk_trion_pll_disable,
		.is_enabled = clk_trion_pll_is_enabled,
		.recalc_rate = clk_trion_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_trion_pll_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_trion_pll_ops);

		const struct clk_ops clk_trion_fixed_pll_ops = {
		.enable = clk_trion_pll_enable,
		.disable = clk_trion_pll_disable,
		.is_enabled = clk_trion_pll_is_enabled,
		.recalc_rate = clk_trion_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		};
		EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);

		static unsigned long
		clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		{
		@@ -539,3 +888,84 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = {
		.set_rate = clk_alpha_pll_postdiv_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);

		static unsigned long clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
		u32 i, div = 1, val;

		if (!pll->post_div_table) {
		pr_err("Missing the post_div_table for the PLL\n");
		return -EINVAL;
		}

		regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_USER_CTL, &val);

		val >>= pll->post_div_shift;
		val &= PLL_POST_DIV_MASK;

		for (i = 0; i < pll->num_post_div; i++) {
		if (pll->post_div_table[i].val == val) {
		div = pll->post_div_table[i].div;
		break;
		}
		}

		return (parent_rate / div);
		}

		static long clk_trion_pll_postdiv_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *prate)
		{
		struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

		if (!pll->post_div_table)
		return -EINVAL;

		return divider_round_rate(hw, rate, prate, pll->post_div_table,
		pll->width, CLK_DIVIDER_ROUND_CLOSEST);
		}

		static int clk_trion_pll_postdiv_set_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate)
		{
		struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
		int i, val = 0, div, ret;

		/*
		* If the PLL is in FSM mode, then treat the set_rate callback
		* as a no-operation.
		*/
		ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &val);
		if (ret)
		return ret;

		if (val & PLL_VOTE_FSM_ENA)
		return 0;

		if (!pll->post_div_table) {
		pr_err("Missing the post_div_table for the PLL\n");
		return -EINVAL;
		}

		div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
		for (i = 0; i < pll->num_post_div; i++) {
		if (pll->post_div_table[i].div == div) {
		val = pll->post_div_table[i].val;
		break;
		}
		}

		return regmap_update_bits(pll->clkr.regmap,
		pll->offset + TRION_PLL_USER_CTL,
		PLL_POST_DIV_MASK << pll->post_div_shift,
		val << pll->post_div_shift);
		}

		const struct clk_ops clk_trion_pll_postdiv_ops = {
		.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
		.round_rate = clk_trion_pll_postdiv_round_rate,
		.set_rate = clk_trion_pll_postdiv_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);

drivers/clk/qcom/clk-alpha-pll.h

+22 −2

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -23,14 +23,22 @@ struct pll_vco {
		u32 val;
		};

		enum pll_type {
		ALPHA_PLL,
		TRION_PLL,
		};

		/**
		* struct clk_alpha_pll - phase locked loop (PLL)
		* @offset: base address of registers
		* @inited: flag that's set when the PLL is initialized
		* @vco_table: array of VCO settings
		* @clkr: regmap clock handle
		*/
		struct clk_alpha_pll {
		u32 offset;
		struct alpha_pll_config *config;
		bool inited;

		const struct pll_vco *vco_table;
		size_t num_vco;
		@@ -40,18 +48,24 @@ struct clk_alpha_pll {
		u8 flags;

		struct clk_regmap clkr;
		enum pll_type type;
		};

		/**
		* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
		* @offset: base address of registers
		* @width: width of post-divider
		* @post_div_shift: shift to differentiate between odd and even post-divider
		* @post_div_table: table with PLL odd and even post-divider settings
		* @num_post_div: Number of PLL post-divider settings
		* @clkr: regmap clock handle
		*/
		struct clk_alpha_pll_postdiv {
		u32 offset;
		u8 width;

		int post_div_shift;
		const struct clk_div_table *post_div_table;
		size_t num_post_div;
		struct clk_regmap clkr;
		};

		@@ -60,6 +74,7 @@ struct alpha_pll_config {
		u32 alpha;
		u32 config_ctl_val;
		u32 config_ctl_hi_val;
		u32 config_ctl_hi1_val;
		u32 main_output_mask;
		u32 aux_output_mask;
		u32 aux2_output_mask;
		@@ -75,8 +90,13 @@ struct alpha_pll_config {
		extern const struct clk_ops clk_alpha_pll_ops;
		extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
		extern const struct clk_ops clk_alpha_pll_postdiv_ops;
		extern const struct clk_ops clk_trion_pll_ops;
		extern const struct clk_ops clk_trion_fixed_pll_ops;
		extern const struct clk_ops clk_trion_pll_postdiv_ops;

		void clk_alpha_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config);
		int clk_trion_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config);

		#endif

include/linux/clk-provider.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -842,6 +842,8 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,

		unsigned long clk_aggregate_rate(struct clk_hw *hw,
		const struct clk_core *parent);
		int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate);
		void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate);

		static inline void __clk_hw_set_clk(struct clk_hw dst, struct clk_hw src)
		{