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Commit 1cafd347 authored by Zou Nan hai's avatar Zou Nan hai Committed by Eric Anholt
Browse files

drm/i915 invalidate indirect state pointers at end of ring exec 



This is required by the spec, and without this some 3D programs will
hang after resume from RC6 we enable that.

Signed-off-by: default avatarZou Nan hai <nanhai.zou@intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent e78d73b1

drivers/gpu/drm/i915/i915_dma.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -499,6 +499,13 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, 
		}

		}

	}

	}







	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

		BEGIN_LP_RING(2);

		OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);

		OUT_RING(MI_NOOP);

		ADVANCE_LP_RING();

	}

	i915_emit_breadcrumb(dev);

	i915_emit_breadcrumb(dev);





	return 0;

	return 0;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -170,6 +170,7 @@ 
#define   MI_NO_WRITE_FLUSH	(1 << 2)

#define   MI_NO_WRITE_FLUSH	(1 << 2)

#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */

#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11,0)

#define MI_OVERLAY_FLIP		MI_INSTR(0x11,0)

drivers/gpu/drm/i915/intel_ringbuffer.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -535,7 +535,16 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev, 
		intel_ring_advance(dev, ring);

		intel_ring_advance(dev, ring);

	}

	}





	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

		intel_ring_begin(dev, ring, 2);

		intel_ring_emit(dev, ring, MI_FLUSH |

				MI_NO_WRITE_FLUSH |

				MI_INVALIDATE_ISP );

		intel_ring_emit(dev, ring, MI_NOOP);

		intel_ring_advance(dev, ring);

	}

	/* XXX breadcrumb */

	/* XXX breadcrumb */



	return 0;

	return 0;

}

}