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Commit 1c5c784d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: add force_clk_lane_hs support" into dev/msm-4.14-display

parents 15c45912 ca9b6f1b

Documentation/devicetree/bindings/display/msm/dsi.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -127,6 +127,7 @@ Optional properties: 
					turns off PHY pmic power supply, phy ldo and DSI Lane ldo during

					turns off PHY pmic power supply, phy ldo and DSI Lane ldo during

					idle screen (footswitch control off) when this property is enabled.

					idle screen (footswitch control off) when this property is enabled.

- qcom,dsi-phy-regulator-min-datarate-bps:  Minimum per lane data rate (bps) to turn on PHY regulator.

- qcom,dsi-phy-regulator-min-datarate-bps:  Minimum per lane data rate (bps) to turn on PHY regulator.

- qcom,panel-force-clock-lane-hs:	A boolean property indicates that panel needs clock lanes in HS mode only





[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/graph.txt

[2] Documentation/devicetree/bindings/graph.txt
@@ -237,4 +238,5 @@ Example: 
		qcom,dsi-phy-regulator-ldo-mode;

		qcom,dsi-phy-regulator-ldo-mode;

		qcom,panel-allow-phy-poweroff;

		qcom,panel-allow-phy-poweroff;

		qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;

		qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;

		qcom,panel-force-clock-lane-hs;

	};
 
	};

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -455,6 +455,11 @@ void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl, 
	/* Disable Timing double buffering */

	/* Disable Timing double buffering */

	DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);

	DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);





	if (cfg->force_clk_lane_hs) {

		reg = DSI_R32(ctrl, DSI_LANE_CTRL);

		reg |= BIT(28);

		DSI_W32(ctrl, DSI_LANE_CTRL, reg);

	}





	pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index);

	pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index);

}

}

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -451,6 +451,7 @@ struct dsi_video_engine_cfg { 
	bool hsa_lp11_en;

	bool hsa_lp11_en;

	bool eof_bllp_lp11_en;

	bool eof_bllp_lp11_en;

	bool bllp_lp11_en;

	bool bllp_lp11_en;

	bool force_clk_lane_hs;

	enum dsi_video_traffic_mode traffic_mode;

	enum dsi_video_traffic_mode traffic_mode;

	u32 vc_id;

	u32 vc_id;

};

};

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -1193,6 +1193,9 @@ static int dsi_panel_parse_video_host_config(struct dsi_video_engine_cfg *cfg, 
	cfg->bllp_lp11_en = utils->read_bool(utils->data,

	cfg->bllp_lp11_en = utils->read_bool(utils->data,

					"qcom,mdss-dsi-bllp-power-mode");

					"qcom,mdss-dsi-bllp-power-mode");





	cfg->force_clk_lane_hs = of_property_read_bool(utils->data,

					"qcom,mdss-dsi-force-clock-lane-hs");



	traffic_mode = utils->get_property(utils->data,

	traffic_mode = utils->get_property(utils->data,

				       "qcom,mdss-dsi-traffic-mode",

				       "qcom,mdss-dsi-traffic-mode",

				       NULL);

				       NULL);

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -311,6 +311,9 @@ static int dsi_phy_settings_init(struct platform_device *pdev, 
			"qcom,dsi-phy-regulator-min-datarate-bps",

			"qcom,dsi-phy-regulator-min-datarate-bps",

			&phy->regulator_min_datarate_bps);

			&phy->regulator_min_datarate_bps);





	phy->cfg.force_clk_lane_hs = of_property_read_bool(pdev->dev.of_node,

			"qcom,panel-force-clock-lane-hs");



	return 0;

	return 0;

err:

err:

	lane->count_per_lane = 0;

	lane->count_per_lane = 0;