Loading arch/arm64/boot/dts/qcom/sdmmagpie-camera.dtsi +32 −0 Original line number Diff line number Diff line Loading @@ -646,4 +646,36 @@ <600000000 0 0>; status = "ok"; }; qcom,cam-lrme { compatible = "qcom,cam-lrme"; arch-compat = "lrme"; status = "ok"; }; cam_lrme: qcom,lrme@ac6b000 { cell-index = <0>; compatible = "qcom,lrme"; reg-names = "lrme"; reg = <0xac6b000 0xa00>; reg-cam-base = <0x6b000>; interrupt-names = "lrme"; interrupts = <0 476 0>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "lrme_clk_src", "lrme_clk"; clocks = <&clock_camcc CAM_CC_LRME_CLK_SRC>, <&clock_camcc CAM_CC_LRME_CLK>; clock-rates = <240000000 0>, <300000000 0>, <320000000 0>, <400000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "lrme_clk_src"; status = "ok"; }; }; Loading
arch/arm64/boot/dts/qcom/sdmmagpie-camera.dtsi +32 −0 Original line number Diff line number Diff line Loading @@ -646,4 +646,36 @@ <600000000 0 0>; status = "ok"; }; qcom,cam-lrme { compatible = "qcom,cam-lrme"; arch-compat = "lrme"; status = "ok"; }; cam_lrme: qcom,lrme@ac6b000 { cell-index = <0>; compatible = "qcom,lrme"; reg-names = "lrme"; reg = <0xac6b000 0xa00>; reg-cam-base = <0x6b000>; interrupt-names = "lrme"; interrupts = <0 476 0>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "lrme_clk_src", "lrme_clk"; clocks = <&clock_camcc CAM_CC_LRME_CLK_SRC>, <&clock_camcc CAM_CC_LRME_CLK>; clock-rates = <240000000 0>, <300000000 0>, <320000000 0>, <400000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "lrme_clk_src"; status = "ok"; }; };