Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (1a0d1e8c) · Commits · e / devices / android_kernel_xiaomi_sm6125

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+3 −2

Original line number	Diff line number	Diff line
		@@ -40,7 +40,7 @@
		pins = "gpio130";
		drive-strength = <8>;
		bias-disable = <0>;
		output-low;
		output-high;
		};
		};
		};
		@@ -128,6 +128,7 @@
		regulator-enable-ramp-delay = <233>;
		gpio = <&tlmm 130 0>;
		enable-active-high;
		regulator-boot-on;
		pinctrl-names = "default";
		pintctrl-0 = <&display_panel_avdd_eldo_default>;
		};
		@@ -672,7 +673,7 @@
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07
		07 04 03 04 00 16 16];
		qcom,display-topology = <1 1 1>;
		qcom,display-topology = <2 1 1>;
		qcom,default-topology-index = <0>;
		};
		};

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+24 −4

Original line number	Diff line number	Diff line
		@@ -191,6 +191,7 @@
		#define PHY_CMN_CTRL_0 0x024
		#define PHY_CMN_CTRL_3 0x030
		#define PHY_CMN_PLL_CNTRL 0x03C
		#define PHY_CMN_GLBL_DIGTOP_SPARE4 0x128

		/* Bit definition of SSC control registers */
		#define SSC_CENTER BIT(0)
		@@ -880,10 +881,24 @@ static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc)
		u32 data;

		MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_3, 0x04);

		data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
		MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data \| BIT(5)));
		}

		static void dsi_pll_phy_dig_reset(struct mdss_pll_resources *rsc)
		{
		/*
		* Reset the PHY digital domain. This would be needed when
		* coming out of a CX or analog rail power collapse while
		* ensuring that the pads maintain LP00 or LP11 state
		*/
		MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
		wmb(); /* Ensure that the reset is asserted */
		MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
		wmb(); /* Ensure that the reset is deasserted */
		}

		static int dsi_pll_enable(struct dsi_pll_vco_clk *vco)
		{
		int rc;
		@@ -917,13 +932,18 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco)

		rsc->pll_on = true;

		dsi_pll_enable_global_clk(rsc);
		/*
		* assert power on reset for PHY digital in case the PLL is
		* enabled after CX of analog domain power collapse. This needs
		* to be done before enabling the global clk.
		*/
		dsi_pll_phy_dig_reset(rsc);
		if (rsc->slave)
		dsi_pll_enable_global_clk(rsc->slave);
		dsi_pll_phy_dig_reset(rsc->slave);

		MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0x01);
		dsi_pll_enable_global_clk(rsc);
		if (rsc->slave)
		MDSS_PLL_REG_W(rsc->slave->phy_base, PHY_CMN_RBUF_CTRL, 0x01);
		dsi_pll_enable_global_clk(rsc->slave);

		error:
		return rc;

drivers/gpu/drm/msm/msm_gem.c

+11 −5

Original line number	Diff line number	Diff line
		@@ -323,14 +323,20 @@ uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj)
		dma_addr_t msm_gem_get_dma_addr(struct drm_gem_object *obj)
		{
		struct msm_gem_object *msm_obj = to_msm_bo(obj);
		struct drm_device *dev = obj->dev;
		struct sg_table *sgt;

		if (IS_ERR_OR_NULL(msm_obj->sgt)) {
		dev_err(dev->dev, "invalid scatter/gather table\n");
		if (!msm_obj->sgt) {
		sgt = dma_buf_map_attachment(obj->import_attach,
		DMA_BIDIRECTIONAL);
		if (IS_ERR_OR_NULL(sgt)) {
		DRM_ERROR("dma_buf_map_attachment failure, err=%d\n",
		PTR_ERR(sgt));
		return 0;
		}
		msm_obj->sgt = sgt;
		}

		return sg_dma_address(msm_obj->sgt->sgl);
		return sg_phys(msm_obj->sgt->sgl);
		}

		static struct msm_gem_vma add_vma(struct drm_gem_object obj,

drivers/gpu/drm/msm/msm_smmu.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -249,7 +249,7 @@ static int msm_smmu_map_dma_buf(struct msm_mmu mmu, struct sg_table sgt,
		&sgt->sgl->dma_address, sgt->sgl->dma_length,
		dir, attrs);
		SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length,
		dir, attrs);
		dir, attrs, client->secure);
		}

		return 0;
		@@ -272,7 +272,7 @@ static void msm_smmu_unmap_dma_buf(struct msm_mmu mmu, struct sg_table sgt,
		&sgt->sgl->dma_address, sgt->sgl->dma_length,
		dir);
		SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length,
		dir);
		dir, client->secure);
		}

		if (!(flags & MSM_BO_EXTBUF))

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+14 −9

Original line number	Diff line number	Diff line
		@@ -389,7 +389,6 @@ static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,

		c = &ctx->hw;

		if (enable) {
		if ((rect_mode == SDE_SSPP_RECT_SOLO)
		\|\| (rect_mode == SDE_SSPP_RECT_0))
		secure_bit_mask =
		@@ -398,10 +397,16 @@ static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,
		secure_bit_mask = 0xA;

		secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);

		if (enable)
		secure \|= secure_bit_mask;
		}
		else
		secure &= ~secure_bit_mask;

		SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);

		/* multiple planes share same sw_status register */
		wmb();
		}