Commit 1918ad77 authored Apr 23, 2010 by Jesse Barnes Committed by Linus Torvalds Apr 23, 2010

drm/i915: fix non-Ironlake 965 class crashes



My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was
testing a whole set of patches together and missed a conversion to the
new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake
965 class chips.  Fortunately, the fix is trivial and has been tested.

Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or
we'll end up reading the wrong graphics memory, likely causing hangs,
crashes, or worse.

Reported-by: Zdenek Kabelac <zdenek.kabelac@gmail.com>
Reported-by: Toralf Förster <toralf.foerster@gmx.de>
Tested-by: Toralf Förster <toralf.foerster@gmx.de>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

parent d5a30458

drivers/gpu/drm/i915/i915_gem.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1793,7 +1793,7 @@ i915_get_gem_seqno(struct drm_device *dev)
		{
		drm_i915_private_t *dev_priv = dev->dev_private;

		if (IS_I965G(dev))
		if (HAS_PIPE_CONTROL(dev))
		return ((volatile u32 *)(dev_priv->seqno_page))[0];
		else
		return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);