Loading drivers/clk/meson/gxbb.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -234,7 +234,7 @@ #define CLKID_HDMI_PCLK 63 #define CLKID_HDMI_PCLK 63 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_USB0_DDR_BRIDGE 65 /* CLKID_MMC_PCLK */ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_DVIN 67 #define CLKID_UART2 68 #define CLKID_UART2 68 #define CLKID_SANA 69 #define CLKID_SANA 69 Loading include/dt-bindings/clock/gxbb-clkc.h +0 −1 Original line number Original line Diff line number Diff line Loading @@ -8,6 +8,5 @@ #define CLKID_CPUCLK 1 #define CLKID_CPUCLK 1 #define CLKID_CLK81 12 #define CLKID_CLK81 12 #define CLKID_ETH 36 #define CLKID_ETH 36 #define CLKID_MMC_PCLK 66 #endif /* __GXBB_CLKC_H */ #endif /* __GXBB_CLKC_H */ Loading
drivers/clk/meson/gxbb.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -234,7 +234,7 @@ #define CLKID_HDMI_PCLK 63 #define CLKID_HDMI_PCLK 63 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_USB0_DDR_BRIDGE 65 /* CLKID_MMC_PCLK */ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_DVIN 67 #define CLKID_UART2 68 #define CLKID_UART2 68 #define CLKID_SANA 69 #define CLKID_SANA 69 Loading
include/dt-bindings/clock/gxbb-clkc.h +0 −1 Original line number Original line Diff line number Diff line Loading @@ -8,6 +8,5 @@ #define CLKID_CPUCLK 1 #define CLKID_CPUCLK 1 #define CLKID_CLK81 12 #define CLKID_CLK81 12 #define CLKID_ETH 36 #define CLKID_ETH 36 #define CLKID_MMC_PCLK 66 #endif /* __GXBB_CLKC_H */ #endif /* __GXBB_CLKC_H */