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Commit 132b1632 authored by Russell King's avatar Russell King
Browse files

ARM: AT91: update clock source registration



In d7e81c26 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants.  Switch over to using this new interface.

Acked-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 40cc5244
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+1 −3
Original line number Diff line number Diff line
@@ -101,7 +101,6 @@ static struct clocksource clk32k = {
	.rating		= 150,
	.read		= read_clk32k,
	.mask		= CLOCKSOURCE_MASK(20),
	.shift		= 10,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

@@ -201,8 +200,7 @@ void __init at91rm9200_timer_init(void)
	clockevents_register_device(&clkevt);

	/* register clocksource */
	clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
	clocksource_register(&clk32k);
	clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
}

struct sys_timer at91rm9200_timer = {
+1 −3
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ static struct clocksource pit_clk = {
	.name		= "pit",
	.rating		= 175,
	.read		= read_pit_clk,
	.shift		= 20,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

@@ -163,10 +162,9 @@ static void __init at91sam926x_pit_init(void)
	 * Register clocksource.  The high order bits of PIV are unused,
	 * so this isn't a 32-bit counter unless we get clockevent irqs.
	 */
	pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
	bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
	pit_clk.mask = CLOCKSOURCE_MASK(bits);
	clocksource_register(&pit_clk);
	clocksource_register_hz(&pit_clk, pit_rate);

	/* Set up irq handler */
	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);