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Commit 10d45d06 authored by Diptanshu Jamgade's avatar Diptanshu Jamgade Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add HALT_DELAY for gpu_cc_cx_gfx3d_clk for SM6150 



CBCR for gpu_cc_cx_ahb_clk does not toggle according to the
clock on/off status. Hence, add HALT_DELAY to stop polling
for clock_off bit.
Also, update the parent of cx_gfx3d_clk
from gpu_cc_gx_gfx3d_clk_src to gpu_cc_gx_gfx_clk as the
RCG enable HW signal is tied to this clock.

Change-Id: I75f447627e294b45e2316624729fb403850d2a3e
Signed-off-by: default avatarDiptanshu Jamgade <djamgade@codeaurora.org>
parent 6836173e

drivers/clk/qcom/gpucc-sm6150.c

+2 −2
Original line number Diff line number Diff line
@@ -296,14 +296,14 @@ static struct clk_branch gpu_cc_cx_apb_clk = { 


static struct clk_branch gpu_cc_cx_gfx3d_clk = {

	.halt_reg = 0x10a4,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x10a4,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gfx3d_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gx_gfx3d_clk_src",

				"gpu_cc_gx_gfx3d_clk",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,