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Commit 0fca060f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I1e241ca0,I60b8f84e,I8f8bcec8 into msm-4.14 

* changes:
  msm: kgsl: Don't set device state to AWARE if GMU recover fails
  msm: kgsl: Add quirk support to use alternative secure context bank
  msm: kgsl: Add a check for valid frequency of RBBM timer clock
parents a0d95aef 28734109

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −0
Original line number Diff line number Diff line
@@ -207,6 +207,9 @@ GPU Quirks: 
- qcom,gpu-quirk-limit-uche-gbif-rw:

				Limit number of read and write transactions from UCHE block to

				GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.

- qcom,gpu-quirk-mmu-secure-cb-alt:

				Select alternate secure context bank to generate SID1 for

				secure playback.



KGSL Memory Pools:

- qcom,gpu-mempools:		Container for sets of GPU mempools.Multiple sets

drivers/gpu/msm/adreno.c

+1 −0
Original line number Diff line number Diff line
@@ -744,6 +744,7 @@ static struct { 
	{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },

	{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,

			"qcom,gpu-quirk-limit-uche-gbif-rw" },

	{ ADRENO_QUIRK_MMU_SECURE_CB_ALT, "qcom,gpu-quirk-mmu-secure-cb-alt" },

};



static struct device_node *

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -150,6 +150,8 @@ 
 * between GBIF, SMMU and MEMNOC.

 */

#define ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW BIT(8)

/* Select alternate secure context bank for mmu */

#define ADRENO_QUIRK_MMU_SECURE_CB_ALT BIT(9)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0

drivers/gpu/msm/kgsl_iommu.c

+11 −2
Original line number Diff line number Diff line
@@ -2521,6 +2521,7 @@ static const struct { 
} kgsl_iommu_cbs[] = {

	{ KGSL_IOMMU_CONTEXT_USER, "gfx3d_user", },

	{ KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure" },

	{ KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure_alt" },

};



static int _kgsl_iommu_cb_probe(struct kgsl_device *device,
@@ -2528,12 +2529,20 @@ static int _kgsl_iommu_cb_probe(struct kgsl_device *device, 
{

	struct platform_device *pdev = of_find_device_by_node(node);

	struct kgsl_iommu_context *ctx = NULL;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	int i;



	for (i = 0; i < ARRAY_SIZE(kgsl_iommu_cbs); i++) {

		if (!strcmp(node->name, kgsl_iommu_cbs[i].name)) {

			int id = kgsl_iommu_cbs[i].id;



			if (ADRENO_QUIRK(adreno_dev,

				ADRENO_QUIRK_MMU_SECURE_CB_ALT)) {

				if (!strcmp(node->name, "gfx3d_secure"))

					continue;

			} else if (!strcmp(node->name, "gfx3d_secure_alt"))

				continue;



			ctx = &iommu->ctx[id];

			ctx->id = id;

			ctx->cb_num = -1;
@@ -2544,8 +2553,8 @@ static int _kgsl_iommu_cb_probe(struct kgsl_device *device, 
	}



	if (ctx == NULL) {

		KGSL_CORE_ERR("dt: Unknown context label %s\n", node->name);

		return -EINVAL;

		KGSL_CORE_ERR("dt: Unused context label %s\n", node->name);

		return 0;

	}



	if (ctx->id == KGSL_IOMMU_CONTEXT_SECURE)

drivers/gpu/msm/kgsl_pwrctrl.c

+9 −7
Original line number Diff line number Diff line
@@ -2241,7 +2241,7 @@ static bool pwrlevel_uses_ib(struct msm_bus_scale_pdata *bus_scale_table, 


int kgsl_pwrctrl_init(struct kgsl_device *device)

{

	int i, k, m, n = 0, result;

	int i, k, m, n = 0, result, freq;

	struct platform_device *pdev = device->pdev;

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct device_node *ocmem_bus_node;
@@ -2288,7 +2288,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
	pwr->wakeup_maxpwrlevel = 0;



	for (i = 0; i < pwr->num_pwrlevels; i++) {

		unsigned int freq = pwr->pwrlevels[i].gpu_freq;

		freq = pwr->pwrlevels[i].gpu_freq;



		if (freq > 0)

			freq = clk_round_rate(pwr->grp_clks[0], freq);
@@ -2299,11 +2299,10 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 


	kgsl_clk_set_rate(device, pwr->num_pwrlevels - 1);



	if (pwr->grp_clks[6] != NULL)

	freq = clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ);

	if (freq > 0)

		kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[6],

			clk_round_rate(pwr->grp_clks[6],

			KGSL_RBBMTIMER_CLK_FREQ),

			clocks[6]);

			freq, clocks[6]);



	_isense_clk_set_rate(pwr, pwr->num_pwrlevels - 1);
@@ -2770,6 +2769,7 @@ _aware(struct kgsl_device *device) 
{

	int status = 0;

	struct gmu_device *gmu = &device->gmu;

	unsigned int state = device->state;



	switch (device->state) {

	case KGSL_STATE_RESET:
@@ -2816,13 +2816,15 @@ _aware(struct kgsl_device *device) 
				WARN_ONCE(1, "Failed to recover GMU\n");

				if (device->snapshot)

					device->snapshot->recovered = false;

				kgsl_pwrctrl_set_state(device, state);

			} else {

				if (device->snapshot)

					device->snapshot->recovered = true;

				kgsl_pwrctrl_set_state(device,

					KGSL_STATE_AWARE);

			}



			clear_bit(GMU_FAULT, &gmu->flags);

			kgsl_pwrctrl_set_state(device, KGSL_STATE_AWARE);

			return status;

		}