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Commit 0f90e9f9 authored by Jayant Shekhar's avatar Jayant Shekhar
Browse files

drm/msm/dsi-staging: update dsi pclk timing calculation 



Update dsi pclk timing calculation based on hardware
recommended settings. Command mode panels need to account
for margin and video mode panels only uses DSC compression
on horizontal active region.

Change-Id: I9c1b8d85ad1f3079e1e8549d192f8293d7cfe299
Signed-off-by: default avatarJayant Shekhar <jshekhar@codeaurora.org>
parent 3dd08f47

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+15 −3
Original line number Original line Diff line number Diff line
@@ -40,6 +40,9 @@ 
#define TO_ON_OFF(x) ((x) ? "ON" : "OFF")

#define TO_ON_OFF(x) ((x) ? "ON" : "OFF")





#define CEIL(x, y)              (((x) + ((y)-1)) / (y))

#define CEIL(x, y)              (((x) + ((y)-1)) / (y))



#define TICKS_IN_MICRO_SECOND    1000000



/**

/**

 * enum dsi_ctrl_driver_ops - controller driver ops

 * enum dsi_ctrl_driver_ops - controller driver ops

 */

 */
@@ -831,6 +834,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	int rc = 0;

	int rc = 0;

	u32 num_of_lanes = 0;

	u32 num_of_lanes = 0;

	u32 bpp;

	u32 bpp;

	u32 refresh_rate = TICKS_IN_MICRO_SECOND;

	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,

	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,

	    byte_clk_rate;

	    byte_clk_rate;

	struct dsi_host_common_cfg *host_cfg = &config->common_config;

	struct dsi_host_common_cfg *host_cfg = &config->common_config;
@@ -853,9 +857,17 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
		num_of_lanes = split_link->lanes_per_sublink;

		num_of_lanes = split_link->lanes_per_sublink;





	if (config->bit_clk_rate_hz_override == 0) {

	if (config->bit_clk_rate_hz_override == 0) {

		if (config->panel_mode == DSI_OP_CMD_MODE) {

			h_period = DSI_H_ACTIVE_DSC(timing);

			v_period = timing->v_active;



			do_div(refresh_rate, timing->mdp_transfer_time_us);

		} else {

			h_period = DSI_H_TOTAL_DSC(timing);

			h_period = DSI_H_TOTAL_DSC(timing);

			v_period = DSI_V_TOTAL(timing);

			v_period = DSI_V_TOTAL(timing);

		bit_rate = h_period * v_period * timing->refresh_rate * bpp;

			refresh_rate = timing->refresh_rate;

		}

		bit_rate = h_period * v_period * refresh_rate * bpp;

	} else {

	} else {

		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;

		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;

	}

	}

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+10 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,16 @@ 
		value;\

		value;\

	})

	})





#define DSI_H_ACTIVE_DSC(t) \

	({\

		u64 value;\

		if ((t)->dsc_enabled && (t)->dsc)\

			value = (t)->dsc->pclk_per_line;\

		else\

			value = (t)->h_active;\

		value;\

	})



#define DSI_DEBUG_NAME_LEN		32

#define DSI_DEBUG_NAME_LEN		32

#define display_for_each_ctrl(index, display) \

#define display_for_each_ctrl(index, display) \

	for (index = 0; (index < (display)->ctrl_count) &&\

	for (index = 0; (index < (display)->ctrl_count) &&\