ARM: dts: msm: Correct GPU iommu protection range for SM8150

GPU iommu registers on SM8150 starts at offset 0xA0000. Correct
the GPU iommu base offset to make sure iommu registers are
protected.

This also corrects GPU iommu context banks start offset and
removes property qcom,micro-mmu-control which is not needed
on SM8150.

Change-Id: I76c1e2c43a12132b4624ca1202d36d6423754ccf
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>