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Commit 0d456bad authored by Max Filippov's avatar Max Filippov Committed by Chris Zankel
Browse files

xtensa: add support for the XTFPGA boards 



The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with
an Xtensa processor and an OpenCores Ethernet device.

Signed-off-by: default avatarChris Zankel <chris@zankel.net>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent da844a81

arch/xtensa/Kconfig

+9 −0
Original line number Original line Diff line number Diff line
@@ -151,6 +151,15 @@ config XTENSA_PLATFORM_S6105 
	select SERIAL_CONSOLE

	select SERIAL_CONSOLE

	select NO_IOPORT

	select NO_IOPORT





config XTENSA_PLATFORM_XTFPGA

	bool "XTFPGA"

	select SERIAL_CONSOLE

	select ETHOC

	select XTENSA_CALIBRATE_CCOUNT

	help

	  XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).

	  This hardware is capable of running a full Linux distribution.



endchoice

endchoice

arch/xtensa/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -38,6 +38,7 @@ endif 
platform-$(CONFIG_XTENSA_PLATFORM_XT2000)	:= xt2000

platform-$(CONFIG_XTENSA_PLATFORM_XT2000)	:= xt2000

platform-$(CONFIG_XTENSA_PLATFORM_ISS)		:= iss

platform-$(CONFIG_XTENSA_PLATFORM_ISS)		:= iss

platform-$(CONFIG_XTENSA_PLATFORM_S6105)	:= s6105

platform-$(CONFIG_XTENSA_PLATFORM_S6105)	:= s6105

platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA)	:= xtfpga





PLATFORM = $(platform-y)

PLATFORM = $(platform-y)

export PLATFORM

export PLATFORM

arch/xtensa/boot/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -23,6 +23,7 @@ subdir-y := lib 




bootdir-$(CONFIG_XTENSA_PLATFORM_ISS)	 += boot-elf

bootdir-$(CONFIG_XTENSA_PLATFORM_ISS)	 += boot-elf

bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot

bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot

bootdir-$(CONFIG_XTENSA_PLATFORM_XTFPGA) += boot-redboot boot-elf boot-uboot









BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o

BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o

arch/xtensa/platforms/xtfpga/Makefile

0 → 100644
+9 −0
Original line number Original line Diff line number Diff line 
# Makefile for the Tensilica xtavnet Emulation Board

#

# Note! Dependencies are done automagically by 'make dep', which also

# removes any old dependencies. DON'T put your own dependencies here

# unless it's something special (ie not a .c file).

#

# Note 2! The CFLAGS definitions are in the main makefile...



obj-y			= setup.o lcd.o

arch/xtensa/platforms/xtfpga/include/platform/hardware.h

0 → 100644
+69 −0
Original line number Original line Diff line number Diff line 
/*

 * arch/xtensa/platform/xtavnet/include/platform/hardware.h

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2006 Tensilica Inc.

 */



/*

 * This file contains the hardware configuration of the XTAVNET boards.

 */



#ifndef __XTENSA_XTAVNET_HARDWARE_H

#define __XTENSA_XTAVNET_HARDWARE_H



/* By default NO_IRQ is defined to 0 in Linux, but we use the

   interrupt 0 for UART... */

#define NO_IRQ                 -1



/* Memory configuration. */



#define PLATFORM_DEFAULT_MEM_START 0x00000000

#define PLATFORM_DEFAULT_MEM_SIZE  0x04000000



/* Interrupt configuration. */



#define PLATFORM_NR_IRQS	10



/* Default assignment of LX60 devices to external interrupts. */



#ifdef CONFIG_ARCH_HAS_SMP

#define DUART16552_INTNUM	XCHAL_EXTINT3_NUM

#define OETH_IRQ		XCHAL_EXTINT4_NUM

#else

#define DUART16552_INTNUM	XCHAL_EXTINT0_NUM

#define OETH_IRQ		XCHAL_EXTINT1_NUM

#endif



/*

 *  Device addresses and parameters.

 */



/* UART */

#define DUART16552_PADDR	(XCHAL_KIO_PADDR + 0x0D050020)

/* LCD instruction and data addresses. */

#define LCD_INSTR_ADDR		((char *)IOADDR(0x0D040000))

#define LCD_DATA_ADDR		((char *)IOADDR(0x0D040004))



/* Misc. */

#define XTFPGA_FPGAREGS_VADDR	IOADDR(0x0D020000)

/* Clock frequency in Hz (read-only):  */

#define XTFPGA_CLKFRQ_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x04)

/* Setting of 8 DIP switches:  */

#define DIP_SWITCHES_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x0C)

/* Software reset (write 0xdead):  */

#define XTFPGA_SWRST_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x10)



/*  OpenCores Ethernet controller:  */

				/* regs + RX/TX descriptors */

#define OETH_REGS_PADDR		(XCHAL_KIO_PADDR + 0x0D030000)

#define OETH_REGS_SIZE		0x1000

#define OETH_SRAMBUFF_PADDR	(XCHAL_KIO_PADDR + 0x0D800000)



				/* 5*rx buffs + 5*tx buffs */

#define OETH_SRAMBUFF_SIZE	(5 * 0x600 + 5 * 0x600)



#endif /* __XTENSA_XTAVNET_HARDWARE_H */