Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0cb9763e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "disp: msm: dsi: Fix pll delay calculation during clock switch"

parents 4213ce67 cf151c97

drivers/gpu/drm/msm/dsi-staging/dsi_clk.h

+4 −4
Original line number Diff line number Diff line
@@ -116,10 +116,10 @@ struct dsi_link_lp_clk_info { 


/**

 * struct link_clk_freq - Clock frequency information for Link clocks

 * @byte_clk_rate:   Frequency of DSI byte_clk in KHz.

 * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in KHz.

 * @pixel_clk_rate:  Frequency of DSI pixel_clk in KHz.

 * @esc_clk_rate:    Frequency of DSI escape clock in KHz.

 * @byte_clk_rate:   Frequency of DSI byte_clk in Hz.

 * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in Hz.

 * @pixel_clk_rate:  Frequency of DSI pixel_clk in Hz.

 * @esc_clk_rate:    Frequency of DSI escape clock in Hz.

 */

struct link_clk_freq {

	u32 byte_clk_rate;

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+1 −1
Original line number Diff line number Diff line
@@ -562,7 +562,7 @@ struct dsi_cmd_engine_cfg { 
 * @common_config:         Host configuration common to both Video and Cmd mode.

 * @video_engine:          Video engine configuration if panel is in video mode.

 * @cmd_engine:            Cmd engine configuration if panel is in cmd mode.

 * @esc_clk_rate_khz:      Esc clock frequency in Hz.

 * @esc_clk_rate_hz:      Esc clock frequency in Hz.

 * @bit_clk_rate_hz:       Bit clock frequency in Hz.

 * @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs.

 * @video_timing:          Video timing information of a frame.

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+4 −4
Original line number Diff line number Diff line
@@ -4031,12 +4031,12 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, 


	cfg = &(m_ctrl->phy->cfg);



	esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000;

	pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) /

	esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;

	pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /

			     esc_clk_rate_hz);

	byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) /

	byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /

			     esc_clk_rate_hz);

	hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) /

	hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /

					esc_clk_rate_hz);



	hsync_period = DSI_H_TOTAL_DSC(&mode->timing);