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Commit 0a2e7bbd authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm/sde: return error for atomic check failures"

parents 2d71a108 387cc75f

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+2 −0
Original line number Diff line number Diff line
@@ -551,6 +551,8 @@ Optional properties: 
					is supported.

- qcom,dsi-dyn-clk-list:		An u32 array which lists all the supported dsi bit clock

					frequencies in Hz for the given panel.

- qcom,dsi-dyn-clk-skip-timing-update:	Boolean to specify whether to skip phy timing parameter

					update during dynamic clock switch.



Required properties for sub-nodes:	None

Optional properties:

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+140 −11
Original line number Diff line number Diff line
@@ -1813,6 +1813,18 @@ static struct clk_fixed_factor dsi0pll_post_vco_div3_5 = { 
	},

};



static struct clk_fixed_factor dsi0pll_shadow_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_shadow_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi0pll_shadow_pll_out_div"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,
@@ -1825,6 +1837,18 @@ static struct clk_fixed_factor dsi1pll_post_vco_div3_5 = { 
	},

};



static struct clk_fixed_factor dsi1pll_shadow_post_vco_div3_5 = {

	.div = 7,

	.mult = 2,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_shadow_post_vco_div3_5",

		.parent_names = (const char *[]){"dsi1pll_shadow_pll_out_div"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi0pll_byteclk_src = {

	.div = 8,

	.mult = 1,
@@ -1885,6 +1909,18 @@ static struct clk_fixed_factor dsi0pll_cphy_byteclk_src = { 
	},

};



static struct clk_fixed_factor dsi0pll_shadow_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_shadow_cphy_byteclk_src",

		.parent_names = (const char *[]){"dsi0pll_shadow_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,
@@ -1897,6 +1933,18 @@ static struct clk_fixed_factor dsi1pll_cphy_byteclk_src = { 
	},

};



static struct clk_fixed_factor dsi1pll_shadow_cphy_byteclk_src = {

	.div = 7,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_cphy_shadow_byteclk_src",

		.parent_names = (const char *[]){"dsi1pll_shadow_bitclk_src"},

		.num_parents = 1,

		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor dsi0pll_post_bit_div = {

	.div = 2,

	.mult = 1,
@@ -1953,8 +2001,9 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = { 
			.name = "dsi0_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi0pll_byteclk_src",

				"dsi0pll_shadow_byteclk_src",

				"dsi0pll_cphy_byteclk_src"},

			.num_parents = 3,

				"dsi0pll_cphy_byteclk_src",

				"dsi0pll_shadow_cphy_byteclk_src"},

			.num_parents = 4,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

				  CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -1970,8 +2019,9 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = { 
			.name = "dsi1_phy_pll_out_byteclk",

			.parent_names = (const char *[]){"dsi1pll_byteclk_src",

				"dsi1pll_shadow_byteclk_src",

				"dsi1pll_cphy_byteclk_src"},

			.num_parents = 3,

				"dsi1pll_cphy_byteclk_src",

				"dsi0pll_shadow_cphy_byteclk_src"},

			.num_parents = 4,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

				  CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2032,6 +2082,23 @@ static struct clk_regmap_mux dsi0pll_cphy_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi0pll_shadow_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_shadow_cphy_pclk_src_mux",

			.parent_names =

				(const char *[]){

					"dsi0pll_shadow_post_vco_div3_5"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_mux dsi1pll_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,
@@ -2085,6 +2152,23 @@ static struct clk_regmap_mux dsi1pll_cphy_pclk_src_mux = { 
	},

};



static struct clk_regmap_mux dsi1pll_shadow_cphy_pclk_src_mux = {

	.reg = PHY_CMN_CLK_CFG1,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_shadow_cphy_pclk_src_mux",

			.parent_names =

				(const char *[]){

					"dsi1pll_shadow_post_vco_div3_5"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_regmap_mux_closest_ops,

		},

	},

};



static struct clk_regmap_div dsi0pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -2130,6 +2214,21 @@ static struct clk_regmap_div dsi0pll_cphy_pclk_src = { 
	},

};



static struct clk_regmap_div dsi0pll_shadow_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_shadow_cphy_pclk_src",

			.parent_names = (const char *[]){

					"dsi0pll_shadow_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_div dsi1pll_pclk_src = {

	.shift = 0,

	.width = 4,
@@ -2175,6 +2274,21 @@ static struct clk_regmap_div dsi1pll_cphy_pclk_src = { 
	},

};



static struct clk_regmap_div dsi1pll_shadow_cphy_pclk_src = {

	.shift = 0,

	.width = 4,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_shadow_cphy_pclk_src",

			.parent_names = (const char *[]){

					"dsi1pll_shadow_cphy_pclk_src_mux"},

			.num_parents = 1,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.ops = &clk_regmap_div_ops,

		},

	},

};



static struct clk_regmap_mux dsi0pll_pclk_mux = {

	.shift = 0,

	.width = 1,
@@ -2183,8 +2297,9 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = { 
			.name = "dsi0_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi0pll_pclk_src",

				"dsi0pll_shadow_pclk_src",

				"dsi0pll_cphy_pclk_src"},

			.num_parents = 3,

				"dsi0pll_cphy_pclk_src",

				"dsi0pll_shadow_cphy_pclk_src"},

			.num_parents = 4,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

				  CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2200,8 +2315,9 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = { 
			.name = "dsi1_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi1pll_pclk_src",

				"dsi1pll_shadow_pclk_src",

				"dsi1pll_cphy_pclk_src"},

			.num_parents = 3,

				"dsi1pll_cphy_pclk_src",

				"dsi1pll_shadow_cphy_pclk_src"},

			.num_parents = 4,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

				  CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,
@@ -2228,10 +2344,15 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { 
	[SHADOW_PLL_OUT_DIV_0_CLK] = &dsi0pll_shadow_pll_out_div.clkr.hw,

	[SHADOW_BITCLK_SRC_0_CLK] = &dsi0pll_shadow_bitclk_src.clkr.hw,

	[SHADOW_BYTECLK_SRC_0_CLK] = &dsi0pll_shadow_byteclk_src.hw,

	[SHADOW_CPHY_BYTECLK_SRC_0_CLK] = &dsi0pll_shadow_cphy_byteclk_src.hw,

	[SHADOW_POST_BIT_DIV_0_CLK] = &dsi0pll_shadow_post_bit_div.hw,

	[SHADOW_POST_VCO_DIV_0_CLK] = &dsi0pll_shadow_post_vco_div.hw,

	[SHADOW_POST_VCO_DIV3_5_0_CLK] = &dsi0pll_shadow_post_vco_div3_5.hw,

	[SHADOW_PCLK_SRC_MUX_0_CLK] = &dsi0pll_shadow_pclk_src_mux.clkr.hw,

	[SHADOW_PCLK_SRC_0_CLK] = &dsi0pll_shadow_pclk_src.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_MUX_0_CLK] =

			&dsi0pll_shadow_cphy_pclk_src_mux.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_0_CLK] = &dsi0pll_shadow_cphy_pclk_src.clkr.hw,

	[VCO_CLK_1] = &dsi1pll_vco_clk.hw,

	[PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,

	[BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
@@ -2250,10 +2371,15 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = { 
	[SHADOW_PLL_OUT_DIV_1_CLK] = &dsi1pll_shadow_pll_out_div.clkr.hw,

	[SHADOW_BITCLK_SRC_1_CLK] = &dsi1pll_shadow_bitclk_src.clkr.hw,

	[SHADOW_BYTECLK_SRC_1_CLK] = &dsi1pll_shadow_byteclk_src.hw,

	[SHADOW_CPHY_BYTECLK_SRC_1_CLK] = &dsi1pll_shadow_cphy_byteclk_src.hw,

	[SHADOW_POST_BIT_DIV_1_CLK] = &dsi1pll_shadow_post_bit_div.hw,

	[SHADOW_POST_VCO_DIV_1_CLK] = &dsi1pll_shadow_post_vco_div.hw,

	[SHADOW_POST_VCO_DIV3_5_1_CLK] = &dsi1pll_shadow_post_vco_div3_5.hw,

	[SHADOW_PCLK_SRC_MUX_1_CLK] = &dsi1pll_shadow_pclk_src_mux.clkr.hw,

	[SHADOW_PCLK_SRC_1_CLK] = &dsi1pll_shadow_pclk_src.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_MUX_1_CLK] =

				&dsi1pll_shadow_cphy_pclk_src_mux.clkr.hw,

	[SHADOW_CPHY_PCLK_SRC_1_CLK] = &dsi1pll_shadow_cphy_pclk_src.clkr.hw,

};



int dsi_pll_clock_register_10nm(struct platform_device *pdev,
@@ -2313,6 +2439,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
		dsi0pll_pclk_src.clkr.regmap = rmap;

		dsi0pll_cphy_pclk_src.clkr.regmap = rmap;

		dsi0pll_shadow_pclk_src.clkr.regmap = rmap;

		dsi0pll_shadow_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);
@@ -2327,6 +2454,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
				&cphy_pclk_src_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);

		dsi0pll_cphy_pclk_src_mux.clkr.regmap = rmap;

		dsi0pll_shadow_cphy_pclk_src_mux.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);
@@ -2335,7 +2463,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
		dsi0pll_vco_clk.priv = pll_res;

		dsi0pll_shadow_vco_clk.priv = pll_res;



		for (i = VCO_CLK_0; i <= SHADOW_PCLK_SRC_0_CLK; i++) {

		for (i = VCO_CLK_0; i <= SHADOW_CPHY_PCLK_SRC_0_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_10nm[i]);

			if (IS_ERR(clk)) {
@@ -2366,6 +2494,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
		dsi1pll_pclk_src.clkr.regmap = rmap;

		dsi1pll_cphy_pclk_src.clkr.regmap = rmap;

		dsi1pll_shadow_pclk_src.clkr.regmap = rmap;

		dsi1pll_shadow_cphy_pclk_src.clkr.regmap = rmap;



		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);
@@ -2380,7 +2509,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
				&cphy_pclk_src_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);

		dsi1pll_cphy_pclk_src_mux.clkr.regmap = rmap;



		dsi1pll_shadow_cphy_pclk_src_mux.clkr.regmap = rmap;

		rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,

				pll_res, &dsi_pll_10nm_config);

		dsi1pll_byteclk_mux.clkr.regmap = rmap;
@@ -2388,7 +2517,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, 
		dsi1pll_vco_clk.priv = pll_res;

		dsi1pll_shadow_vco_clk.priv = pll_res;



		for (i = VCO_CLK_1; i <= SHADOW_PCLK_SRC_1_CLK; i++) {

		for (i = VCO_CLK_1; i <= SHADOW_CPHY_PCLK_SRC_1_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_10nm[i]);

			if (IS_ERR(clk)) {

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+5 −4
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -67,6 +67,7 @@ int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy, 
 * @host:       DSI host configuration.

 * @timing:     DSI phy lane configurations.

 * @use_mode_bit_clk: Boolean to indicate whether to recalculate bit clk.

 * @is_cphy:	Boolean to indicate whether cphy mode.

 *

 * This function setups the catalog information in the dsi_phy_hw object.

 *
@@ -76,7 +77,7 @@ int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, 
				       struct dsi_mode_info *mode,

				       struct dsi_host_common_cfg *host,

				       struct dsi_phy_per_lane_cfgs *timing,

				       bool use_mode_bit_clk);

				       bool use_mode_bit_clk, bool is_cphy);



/* Definitions for 14nm PHY hardware driver */

void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,
@@ -91,7 +92,7 @@ int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg, 
void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);

void dsi_phy_hw_v2_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);

void dsi_phy_hw_v2_0_dyn_refresh_config(struct dsi_phy_hw *phy,

		struct dsi_phy_cfg *cfg, bool is_master);

		struct dsi_phy_cfg *cfg, bool is_master, bool is_cphy);

void dsi_phy_hw_v2_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,

		struct dsi_dyn_clk_delay *delay);

int dsi_phy_hw_v2_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings,
@@ -262,7 +263,7 @@ void dsi_ctrl_hw_cmn_hs_req_sel(struct dsi_ctrl_hw *ctrl, bool sel_phy); 
/* dynamic refresh specific functions */

void dsi_phy_hw_v3_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);

void dsi_phy_hw_v3_0_dyn_refresh_config(struct dsi_phy_hw *phy,

				struct dsi_phy_cfg *cfg, bool is_master);

		struct dsi_phy_cfg *cfg, bool is_master, bool is_cphy);

void dsi_phy_hw_v3_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy,

					    struct dsi_dyn_clk_delay *delay);

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+70 −22
Original line number Diff line number Diff line
@@ -3018,11 +3018,15 @@ static int dsi_display_clocks_init(struct dsi_display *display) 
	const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";

	const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";

	const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";

	const char *shadow_cphybyte = "shadow_cphybyte",

				*shadow_cphypixel = "shadow_cphypixel";

	struct clk *dsi_clk;

	struct dsi_clk_link_set *src = &display->clock_info.src_clks;

	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;

	struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;

	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;

	struct dsi_clk_link_set *shadow_cphy =

					&display->clock_info.shadow_cphy_clks;

	struct dsi_clk_link_set *xo = &display->clock_info.xo_clks;

	struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
@@ -3079,6 +3083,12 @@ static int dsi_display_clocks_init(struct dsi_display *display) 
				if (dsi_display_check_prefix(shadow_pixel,

							clk_name))

					shadow->pixel_clk = NULL;

				if (dsi_display_check_prefix(shadow_cphybyte,

							clk_name))

					shadow_cphy->byte_clk = NULL;

				if (dsi_display_check_prefix(shadow_cphypixel,

							clk_name))

					shadow_cphy->pixel_clk = NULL;



				dyn_clk_caps->dyn_clk_support = false;

			}
@@ -3123,6 +3133,16 @@ static int dsi_display_clocks_init(struct dsi_display *display) 
			shadow->pixel_clk = dsi_clk;

			continue;

		}



		if (dsi_display_check_prefix(shadow_cphybyte, clk_name)) {

			shadow_cphy->byte_clk = dsi_clk;

			continue;

		}



		if (dsi_display_check_prefix(shadow_cphypixel, clk_name)) {

			shadow_cphy->pixel_clk = dsi_clk;

			continue;

		}

	}



	return 0;
@@ -3943,12 +3963,11 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display, 
			byte_intf_clk_rate = byte_clk_rate;

			do_div(byte_intf_clk_rate, 2);

		} else {

			do_div(bit_rate, bits_per_symbol);

			bit_rate *= num_of_symbols;

			bit_rate_per_lane = bit_rate;

			do_div(bit_rate_per_lane, num_of_lanes);

			byte_clk_rate = bit_rate_per_lane;

			do_div(byte_clk_rate, 7);

			bit_rate_per_lane = bit_clk_rate;

			pclk_rate *= bits_per_symbol;

			do_div(pclk_rate, num_of_symbols);

			byte_clk_rate = bit_clk_rate;

			do_div(byte_clk_rate, num_of_symbols);

			/* For CPHY, byte_intf_clk is same as byte_clk */

			byte_intf_clk_rate = byte_clk_rate;

		}
@@ -4040,6 +4059,17 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 


	m_ctrl = &display->ctrl[display->clk_master_idx];



	if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {

		dsi_clk_prepare_enable(&display->clock_info.cphy_clks);



		rc = dsi_clk_update_parent(

					&display->clock_info.shadow_cphy_clks,

					&display->clock_info.mux_clks);

		if (rc) {

			pr_err("failed update mux parent to shadow\n");

			goto exit;

		}

	} else {

		dsi_clk_prepare_enable(&display->clock_info.src_clks);



		rc = dsi_clk_update_parent(&display->clock_info.shadow_clks,
@@ -4048,6 +4078,7 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
			pr_err("failed update mux parent to shadow\n");

			goto exit;

		}

	}



	display_for_each_ctrl(i, display) {

		ctrl = &display->ctrl[i];
@@ -4093,13 +4124,21 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
		ctrl = &display->ctrl[i];

		dsi_phy_dynamic_refresh_clear(ctrl->phy);

	}

	if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {

		rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,

				&display->clock_info.mux_clks);

		if (rc)

			pr_err("could not switch back to src clks %d\n", rc);



		dsi_clk_disable_unprepare(&display->clock_info.cphy_clks);

	} else {

		rc = dsi_clk_update_parent(&display->clock_info.src_clks,

				&display->clock_info.mux_clks);

		if (rc)

			pr_err("could not switch back to src clks %d\n", rc);



		dsi_clk_disable_unprepare(&display->clock_info.src_clks);

	}



	return rc;
@@ -4135,10 +4174,14 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 
	struct dsi_display_ctrl *m_ctrl, *ctrl;

	struct dsi_dyn_clk_delay delay;

	struct link_clk_freq bkp_freq;

	bool is_cphy;

	struct dsi_dyn_clk_caps *dyn_clk_caps;



	dsi_panel_acquire_panel_lock(display->panel);



	m_ctrl = &display->ctrl[display->clk_master_idx];

	is_cphy = (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) ?

			true : false;



	dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
@@ -4148,9 +4191,13 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 
	dsi_display_mask_ctrl_error_interrupts(display, mask, true);



	/* update the phy timings based on new mode */

	dyn_clk_caps = &display->panel->dyn_clk_caps;

	if (!dyn_clk_caps->skip_phy_timing_update) {

		display_for_each_ctrl(i, display) {

			ctrl = &display->ctrl[i];

		dsi_phy_update_phy_timings(ctrl->phy, &display->config);

			dsi_phy_update_phy_timings(ctrl->phy, &display->config,

				is_cphy);

		}

	}



	/* back up existing rates to handle failure case */
@@ -4174,10 +4221,11 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 
		if (!ctrl->phy)

			continue;

		if (ctrl == m_ctrl)

			dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);

			dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,

				true, is_cphy);

		else

			dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,

						       false);

				false, is_cphy);

	}



	rc = _dsi_display_dyn_update_clks(display, &bkp_freq);

drivers/gpu/drm/msm/dsi-staging/dsi_display.h

+3 −1
Original line number Diff line number Diff line
@@ -114,7 +114,8 @@ struct dsi_display_boot_param { 
 * struct dsi_display_clk_info - dsi display clock source information

 * @src_clks:          Source clocks for DSI display.

 * @mux_clks:          Mux clocks used for DFPS.

 * @shadow_clks:       Used for DFPS.

 * @shadow_clks:       Used for D-phy clock switch

 * @shadow_cphy_clks:  Used for C-phy clock switch

 * @xo_clks:           XO clocks for DSI display

 */

struct dsi_display_clk_info {
@@ -122,6 +123,7 @@ struct dsi_display_clk_info { 
	struct dsi_clk_link_set mux_clks;

	struct dsi_clk_link_set cphy_clks;

	struct dsi_clk_link_set shadow_clks;

	struct dsi_clk_link_set shadow_cphy_clks;

	struct dsi_clk_link_set xo_clks;

};