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Commit 073b8546 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge branch 'for-next' of git://gitorious.org/usb/usb into usb-next 

* 'for-next' of git://gitorious.org/usb/usb: (47 commits)
  usb: musb: Enable DMA mode1 RX for transfers without short packets
  usb: musb: fix build breakage
  usb: gadget: audio: queue wLength-sized requests
  usb: gadget: audio: actually support both speeds
  usb: gadget: storage: make FSG_NUM_BUFFERS variable size
  USB: gadget: storage: remove alignment assumption
  usb: gadget: storage: adapt logic block size to bound block devices
  usb: dwc3: gadget: improve debug on link state change
  usb: dwc3: omap: set idle and standby modes
  usb: dwc3: ep0: introduce ep0_expect_in flag
  usb: dwc3: ep0: giveback requests on stall_and_restart
  usb: dwc3: gadget: drop the useless dma_sync_single* calls
  usb: dwc3: gadget: fix GCTL programming
  usb: dwc3: define ScaleDown macro helper
  usb: dwc3: Fix definition of DWC3_GCTL_U2RSTECN
  usb: dwc3: gadget: do not map/unmap ZLP transfers
  usb: dwc3: omap: fix IRQ handling
  usb: dwc3: omap: change IRQ name to dwc3-omap
  usb: dwc3: add module.h to dwc3-omap.c and core.c
  usb: dwc3: omap: distinguish between SW and HW modes
  ...
parents b5dd18d8 0ae52d54

arch/arm/mach-omap2/Makefile

+5 −6
Original line number Diff line number Diff line
@@ -242,14 +242,11 @@ obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ 
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)	+= board-omap3touchbook.o \

					   hsmmc.o

obj-$(CONFIG_MACH_OMAP_4430SDP)		+= board-4430sdp.o \

					   hsmmc.o \

					   omap_phy_internal.o

					   hsmmc.o

obj-$(CONFIG_MACH_OMAP4_PANDA)		+= board-omap4panda.o \

					   hsmmc.o \

					   omap_phy_internal.o

					   hsmmc.o



obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o \

					   omap_phy_internal.o \

obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o



obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
@@ -260,6 +257,8 @@ obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o 
usbfs-$(CONFIG_ARCH_OMAP_OTG)		:= usb-fs.o

obj-y					+= $(usbfs-m) $(usbfs-y)

obj-y					+= usb-musb.o

obj-y					+= omap_phy_internal.o



obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o

obj-y					+= usb-host.o

drivers/usb/dwc3/core.c

+10 −10
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/slab.h>

#include <linux/spinlock.h>
@@ -241,6 +242,15 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc) 
	u32			reg;

	int			ret;



	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);

	/* This should read as U3 followed by revision number */

	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {

		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");

		ret = -ENODEV;

		goto err0;

	}

	dwc->revision = reg & DWC3_GSNPSREV_MASK;



	dwc3_core_soft_reset(dwc);



	/* issue device SoftReset too */
@@ -260,16 +270,6 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc) 
		cpu_relax();

	} while (true);



	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);

	/* This should read as U3 followed by revision number */

	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {

		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");

		ret = -ENODEV;

		goto err0;

	}



	dwc->revision = reg & DWC3_GSNPSREV_MASK;



	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,

			DWC3_EVENT_BUFFERS_SIZE);

	if (ret) {

drivers/usb/dwc3/core.h

+39 −19
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ 


/* Global Configuration Register */

#define DWC3_GCTL_PWRDNSCALE(n)	(n << 19)

#define DWC3_GCTL_U2RSTECN	16

#define DWC3_GCTL_U2RSTECN	(1 << 16)

#define DWC3_GCTL_RAMCLKSEL(x)	((x & DWC3_GCTL_CLK_MASK) << 6)

#define DWC3_GCTL_CLK_BUS	(0)

#define DWC3_GCTL_CLK_PIPE	(1)
@@ -160,6 +160,7 @@ 
#define DWC3_GCTL_PRTCAP_OTG	3



#define DWC3_GCTL_CORESOFTRESET	(1 << 11)

#define DWC3_GCTL_SCALEDOWN(n)	(n << 4)

#define DWC3_GCTL_DISSCRAMBLE	(1 << 3)



/* Global USB2 PHY Configuration Register */
@@ -348,7 +349,9 @@ struct dwc3_ep { 
#define DWC3_EP_WEDGE		(1 << 2)

#define DWC3_EP_BUSY		(1 << 4)

#define DWC3_EP_PENDING_REQUEST	(1 << 5)

#define DWC3_EP_WILL_SHUTDOWN	(1 << 6)



	/* This last one is specific to EP0 */

#define DWC3_EP0_DIR_IN		(1 << 31)



	unsigned		current_trb;
@@ -368,18 +371,19 @@ enum dwc3_phy { 
	DWC3_PHY_USB2,

};



enum dwc3_ep0_next {

	DWC3_EP0_UNKNOWN = 0,

	DWC3_EP0_COMPLETE,

	DWC3_EP0_NRDY_SETUP,

	DWC3_EP0_NRDY_DATA,

	DWC3_EP0_NRDY_STATUS,

};



enum dwc3_ep0_state {

	EP0_UNCONNECTED		= 0,

	EP0_IDLE,

	EP0_IN_DATA_PHASE,

	EP0_OUT_DATA_PHASE,

	EP0_IN_WAIT_GADGET,

	EP0_OUT_WAIT_GADGET,

	EP0_IN_WAIT_NRDY,

	EP0_OUT_WAIT_NRDY,

	EP0_IN_STATUS_PHASE,

	EP0_OUT_STATUS_PHASE,

	EP0_STALL,

	EP0_SETUP_PHASE,

	EP0_DATA_PHASE,

	EP0_STATUS_PHASE,

};



enum dwc3_link_state {
@@ -503,13 +507,15 @@ static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) 


/**

 * struct dwc3 - representation of our controller

 * ctrl_req: usb control request which is used for ep0

 * ep0_trb: trb which is used for the ctrl_req

 * setup_buf: used while precessing STD USB requests

 * ctrl_req_addr: dma address of ctrl_req

 * ep0_trb: dma address of ep0_trb

 * ep0_usb_req: dummy req used while handling STD USB requests

 * setup_buf_addr: dma address of setup_buf

 * @ctrl_req: usb control request which is used for ep0

 * @ep0_trb: trb which is used for the ctrl_req

 * @ep0_bounce: bounce buffer for ep0

 * @setup_buf: used while precessing STD USB requests

 * @ctrl_req_addr: dma address of ctrl_req

 * @ep0_trb: dma address of ep0_trb

 * @ep0_usb_req: dummy req used while handling STD USB requests

 * @setup_buf_addr: dma address of setup_buf

 * @ep0_bounce_addr: dma address of ep0_bounce

 * @lock: for synchronizing

 * @dev: pointer to our struct device

 * @event_buffer_list: a list of event buffers
@@ -522,6 +528,9 @@ static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) 
 * @is_selfpowered: true when we are selfpowered

 * @three_stage_setup: set if we perform a three phase setup

 * @ep0_status_pending: ep0 status response without a req is pending

 * @ep0_bounced: true when we used bounce buffer

 * @ep0_expect_in: true when we expect a DATA IN transfer

 * @ep0_next_event: hold the next expected event

 * @ep0state: state of endpoint zero

 * @link_state: link state

 * @speed: device speed (super, high, full, low)
@@ -531,10 +540,12 @@ static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) 
struct dwc3 {

	struct usb_ctrlrequest	*ctrl_req;

	struct dwc3_trb_hw	*ep0_trb;

	void			*ep0_bounce;

	u8			*setup_buf;

	dma_addr_t		ctrl_req_addr;

	dma_addr_t		ep0_trb_addr;

	dma_addr_t		setup_buf_addr;

	dma_addr_t		ep0_bounce_addr;

	struct usb_request	ep0_usb_req;

	/* device lock */

	spinlock_t		lock;
@@ -564,7 +575,10 @@ struct dwc3 { 
	unsigned		is_selfpowered:1;

	unsigned		three_stage_setup:1;

	unsigned		ep0_status_pending:1;

	unsigned		ep0_bounced:1;

	unsigned		ep0_expect_in:1;



	enum dwc3_ep0_next	ep0_next_event;

	enum dwc3_ep0_state	ep0state;

	enum dwc3_link_state	link_state;

	enum dwc3_device_state	dev_state;
@@ -634,6 +648,12 @@ struct dwc3_event_depevt { 
#define DEPEVT_STATUS_SHORT     (1 << 1)

#define DEPEVT_STATUS_IOC       (1 << 2)

#define DEPEVT_STATUS_LST	(1 << 3)



/* Control-only Status */

#define DEPEVT_STATUS_CONTROL_SETUP	0

#define DEPEVT_STATUS_CONTROL_DATA	1

#define DEPEVT_STATUS_CONTROL_STATUS	2



	u32	parameters:16;

} __packed;

drivers/usb/dwc3/debugfs.c

+0 −92
Original line number Diff line number Diff line
@@ -406,91 +406,6 @@ static const struct file_operations dwc3_regdump_fops = { 
	.release		= single_release,

};





static int dwc3_send_testmode_cmd(struct dwc3 *dwc, int mode)

{

	u32 timeout = 250;



	dwc3_writel(dwc->regs, DWC3_DGCMDPAR, mode);

	dwc3_writel(dwc->regs, DWC3_DGCMD, DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK |

			DWC3_DEPCMD_CMDACT);

	do {

		u32 reg;



		reg = dwc3_readl(dwc->regs, DWC3_DGCMD);

		if (!(reg & DWC3_DEPCMD_CMDACT))

			return 0;

		timeout--;

		if (!timeout)

			return -ETIMEDOUT;

		mdelay(1);

	} while (1);

}



static struct dwc3_trb_hw trb_0 __aligned(16);

static struct dwc3_trb_hw trb_1 __aligned(16);



#define BUF_SIZE	4096

static int dwc3_testmode_open(struct inode *inode, struct file *file)

{

	struct dwc3 *dwc = inode->i_private;

	struct dwc3_gadget_ep_cmd_params par0;

	struct dwc3_gadget_ep_cmd_params par1;

	struct dwc3_trb         trb;

	int ret;

	u8 *buf0;

	u8 *buf1;



	buf0 = kmalloc(BUF_SIZE, GFP_KERNEL);

	if (!buf0)

		return -ENOMEM;

	buf1 = kmalloc(BUF_SIZE, GFP_KERNEL);

	if (!buf1)

		return -ENOMEM;



	memset(buf0, 0xaa, BUF_SIZE);

	memset(buf1, 0x33, BUF_SIZE);



	memset(&trb, 0, sizeof(trb));

	memset(&par0, 0, sizeof(par0));

	memset(&par1, 0, sizeof(par1));



	trb.lst = 1;

	trb.trbctl = DWC3_TRBCTL_NORMAL;

	trb.length = BUF_SIZE;

	trb.hwo = 1;



	trb.bplh = virt_to_phys(buf0);

	dwc3_trb_to_hw(&trb, &trb_0);



	trb.bplh = virt_to_phys(buf1);

	dwc3_trb_to_hw(&trb, &trb_1);



	par0.param0.depstrtxfer.transfer_desc_addr_high =

		upper_32_bits(virt_to_phys(&trb_0));

	par0.param1.depstrtxfer.transfer_desc_addr_low =

		lower_32_bits(virt_to_phys(&trb_0));



	par1.param0.depstrtxfer.transfer_desc_addr_high =

		upper_32_bits(virt_to_phys(&trb_1));

	par1.param1.depstrtxfer.transfer_desc_addr_low =

		lower_32_bits(virt_to_phys(&trb_1));



	dwc3_send_testmode_cmd(dwc, 1);



	ret = dwc3_send_gadget_ep_cmd(dwc, 0, DWC3_DEPCMD_STARTTRANSFER, &par0);

	ret = dwc3_send_gadget_ep_cmd(dwc, 1, DWC3_DEPCMD_STARTTRANSFER, &par1);



	dwc3_send_testmode_cmd(dwc, 0);

	return -EBUSY;

}



static const struct file_operations dwc3_testmode_fops = {

	.open			= dwc3_testmode_open,

	.read			= seq_read,

	.release		= single_release,

};



int __devinit dwc3_debugfs_init(struct dwc3 *dwc)

{

	struct dentry		*root;
@@ -511,13 +426,6 @@ int __devinit dwc3_debugfs_init(struct dwc3 *dwc) 
		ret = PTR_ERR(file);

		goto err1;

	}

	file = debugfs_create_file("testmode", S_IRUGO, root, dwc,

			&dwc3_testmode_fops);

	if (IS_ERR(file)) {

		ret = PTR_ERR(file);

		goto err1;

	}



	return 0;



err1:

drivers/usb/dwc3/dwc3-omap.c

+73 −82
Original line number Diff line number Diff line
@@ -37,11 +37,13 @@ 
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/slab.h>

#include <linux/interrupt.h>

#include <linux/spinlock.h>

#include <linux/platform_device.h>

#include <linux/platform_data/dwc3-omap.h>

#include <linux/dma-mapping.h>

#include <linux/ioport.h>

#include <linux/io.h>
@@ -74,8 +76,23 @@ 
/* SYSCONFIG REGISTER */

#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)

#define USBOTGSS_SYSCONFIG_STANDBYMODE(x)	((x) << 4)



#define USBOTGSS_STANDBYMODE_FORCE_STANDBY	0

#define USBOTGSS_STANDBYMODE_NO_STANDBY		1

#define USBOTGSS_STANDBYMODE_SMART_STANDBY	2

#define USBOTGSS_STANDBYMODE_SMART_WAKEUP	3



#define USBOTGSS_STANDBYMODE_MASK		(0x03 << 4)



#define USBOTGSS_SYSCONFIG_IDLEMODE(x)		((x) << 2)



#define USBOTGSS_IDLEMODE_FORCE_IDLE		0

#define USBOTGSS_IDLEMODE_NO_IDLE		1

#define USBOTGSS_IDLEMODE_SMART_IDLE		2

#define USBOTGSS_IDLEMODE_SMART_WAKEUP		3



#define USBOTGSS_IDLEMODE_MASK			(0x03 << 2)



/* IRQ_EOI REGISTER */

#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)
@@ -125,106 +142,51 @@ struct dwc3_omap { 
	u32			dma_status:1;

};



#ifdef CONFIG_PM

static int dwc3_omap_suspend(struct device *dev)

{

	struct dwc3_omap	*omap = dev_get_drvdata(dev);



	memcpy_fromio(omap->context, omap->base, omap->resource_size);



	return 0;

}



static int dwc3_omap_resume(struct device *dev)

{

	struct dwc3_omap	*omap = dev_get_drvdata(dev);



	memcpy_toio(omap->base, omap->context, omap->resource_size);



	return 0;

}



static int dwc3_omap_idle(struct device *dev)

{

	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	u32			reg;



	/* stop DMA Engine */

	reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);

	reg &= ~(USBOTGSS_SYSCONFIG_DMADISABLE);

	dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);



	return 0;

}



static UNIVERSAL_DEV_PM_OPS(dwc3_omap_pm_ops, dwc3_omap_suspend,

		dwc3_omap_resume, dwc3_omap_idle);



#define DEV_PM_OPS	(&dwc3_omap_pm_ops)

#else

#define DEV_PM_OPS	NULL

#endif



static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)

{

	struct dwc3_omap	*omap = _omap;

	u32			reg;

	u32			ctrl;



	spin_lock(&omap->lock);



	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);

	ctrl = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL);



	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {

		dev_dbg(omap->base, "DMA Disable was Cleared\n");

		dev_dbg(omap->dev, "DMA Disable was Cleared\n");

		omap->dma_status = false;

	}



	if (reg & USBOTGSS_IRQ1_OEVT)

		dev_dbg(omap->base, "OTG Event\n");

		dev_dbg(omap->dev, "OTG Event\n");



	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) {

		dev_dbg(omap->base, "DRVVBUS Rise\n");

		ctrl |= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;

	}

	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)

		dev_dbg(omap->dev, "DRVVBUS Rise\n");



	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) {

		dev_dbg(omap->base, "CHRGVBUS Rise\n");

		ctrl |= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;

	}

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)

		dev_dbg(omap->dev, "CHRGVBUS Rise\n");



	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) {

		dev_dbg(omap->base, "DISCHRGVBUS Rise\n");

		ctrl |= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;

	}

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)

		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");



	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) {

		dev_dbg(omap->base, "IDPULLUP Rise\n");

		ctrl |= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;

	}

	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)

		dev_dbg(omap->dev, "IDPULLUP Rise\n");



	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) {

		dev_dbg(omap->base, "DRVVBUS Fall\n");

		ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;

	}

	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)

		dev_dbg(omap->dev, "DRVVBUS Fall\n");



	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) {

		dev_dbg(omap->base, "CHRGVBUS Fall\n");

		ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;

	}

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)

		dev_dbg(omap->dev, "CHRGVBUS Fall\n");



	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) {

		dev_dbg(omap->base, "DISCHRGVBUS Fall\n");

		ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;

	}

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)

		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");



	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) {

		dev_dbg(omap->base, "IDPULLUP Fall\n");

		ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;

	}

	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)

		dev_dbg(omap->dev, "IDPULLUP Fall\n");



	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);



	dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL, ctrl);

	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);

	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);



	spin_unlock(&omap->lock);
@@ -233,6 +195,7 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 


static int __devinit dwc3_omap_probe(struct platform_device *pdev)

{

	struct dwc3_omap_data	*pdata = pdev->dev.platform_data;

	struct platform_device	*dwc3;

	struct dwc3_omap	*omap;

	struct resource		*res;
@@ -298,12 +261,41 @@ static int __devinit dwc3_omap_probe(struct platform_device *pdev) 
	omap->base	= base;

	omap->dwc3	= dwc3;



	reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);



	if (!pdata) {

		dev_dbg(&pdev->dev, "missing platform data\n");

	} else {

		switch (pdata->utmi_mode) {

		case DWC3_OMAP_UTMI_MODE_SW:

			reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;

			break;

		case DWC3_OMAP_UTMI_MODE_HW:

			reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;

			break;

		default:

			dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",

					pdata->utmi_mode);

		}

	}



	dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);



	/* check the DMA Status */

	reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);

	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);



	/* Set No-Idle and No-Standby */

	reg &= ~(USBOTGSS_STANDBYMODE_MASK

			| USBOTGSS_IDLEMODE_MASK);



	reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)

		| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));



	dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);



	ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,

			"dwc3-wrapper", omap);

			"dwc3-omap", omap);

	if (ret) {

		dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",

				omap->irq, ret);
@@ -311,10 +303,10 @@ static int __devinit dwc3_omap_probe(struct platform_device *pdev) 
	}



	/* enable all IRQs */

	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x01);

	reg = USBOTGSS_IRQO_COREIRQ_ST;

	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);



	reg = (USBOTGSS_IRQ1_DMADISABLECLR |

			USBOTGSS_IRQ1_OEVT |

	reg = (USBOTGSS_IRQ1_OEVT |

			USBOTGSS_IRQ1_DRVVBUS_RISE |

			USBOTGSS_IRQ1_CHRGVBUS_RISE |

			USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
@@ -388,7 +380,6 @@ static struct platform_driver dwc3_omap_driver = { 
	.remove		= __devexit_p(dwc3_omap_remove),

	.driver		= {

		.name	= "omap-dwc3",

		.pm	= DEV_PM_OPS,

		.of_match_table	= of_dwc3_matach,

	},

};