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Commit 05cf8077 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull networking fixes from David Miller:

 1) Missing device reference in IPSEC input path results in crashes
    during device unregistration.  From Subash Abhinov Kasiviswanathan.

 2) Per-queue ISR register writes not being done properly in macb
    driver, from Cyrille Pitchen.

 3) Stats accounting bugs in bcmgenet, from Patri Gynther.

 4) Lightweight tunnel's TTL and TOS were swapped in netlink dumps, from
    Quentin Armitage.

 5) SXGBE driver has off-by-one in probe error paths, from Rasmus
    Villemoes.

 6) Fix race in save/swap/delete options in netfilter ipset, from
    Vishwanath Pai.

 7) Ageing time of bridge not set properly when not operating over a
    switchdev device.  Fix from Haishuang Yan.

 8) Fix GRO regression wrt nested FOU/GUE based tunnels, from Alexander
    Duyck.

 9) IPV6 UDP code bumps wrong stats, from Eric Dumazet.

10) FEC driver should only access registers that actually exist on the
    given chipset, fix from Fabio Estevam.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (73 commits)
  net: mvneta: fix changing MTU when using per-cpu processing
  stmmac: fix MDIO settings
  Revert "stmmac: Fix 'eth0: No PHY found' regression"
  stmmac: fix TX normal DESC
  net: mvneta: use cache_line_size() to get cacheline size
  net: mvpp2: use cache_line_size() to get cacheline size
  net: mvpp2: fix maybe-uninitialized warning
  tun, bpf: fix suspicious RCU usage in tun_{attach, detach}_filter
  net: usb: cdc_ncm: adding Telit LE910 V2 mobile broadband card
  rtnl: fix msg size calculation in if_nlmsg_size()
  fec: Do not access unexisting register in Coldfire
  net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
  net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
  net: dsa: mv88e6xxx: Clear the PDOWN bit on setup
  net: dsa: mv88e6xxx: Introduce _mv88e6xxx_phy_page_{read, write}
  bpf: make padding in bpf_tunnel_key explicit
  ipv6: udp: fix UDP_MIB_IGNOREDMULTI updates
  bnxt_en: Fix ethtool -a reporting.
  bnxt_en: Fix typo in bnxt_hwrm_set_pause_common().
  bnxt_en: Implement proper firmware message padding.
  ...
parents cf78031a db5dd0db
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+1 −1
Original line number Original line Diff line number Diff line
@@ -386,7 +386,7 @@ used. First phase is to "prepare" anything needed, including various checks,
memory allocation, etc. The goal is to handle the stuff that is not unlikely
memory allocation, etc. The goal is to handle the stuff that is not unlikely
to fail here. The second phase is to "commit" the actual changes.
to fail here. The second phase is to "commit" the actual changes.


Switchdev provides an inftrastructure for sharing items (for example memory
Switchdev provides an infrastructure for sharing items (for example memory
allocations) between the two phases.
allocations) between the two phases.


The object created by a driver in "prepare" phase and it is queued up by:
The object created by a driver in "prepare" phase and it is queued up by:
+10 −5
Original line number Original line Diff line number Diff line
@@ -215,9 +215,11 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
			if (count == 0)
			if (count == 0)
				count = 32;
				count = 32;
			isac_empty_fifo(cs, count);
			isac_empty_fifo(cs, count);
			if ((count = cs->rcvidx) > 0) {
			count = cs->rcvidx;
			if (count > 0) {
				cs->rcvidx = 0;
				cs->rcvidx = 0;
				if (!(skb = alloc_skb(count, GFP_ATOMIC)))
				skb = alloc_skb(count, GFP_ATOMIC);
				if (!skb)
					printk(KERN_WARNING "HiSax: D receive out of memory\n");
					printk(KERN_WARNING "HiSax: D receive out of memory\n");
				else {
				else {
					memcpy(skb_put(skb, count), cs->rcvbuf, count);
					memcpy(skb_put(skb, count), cs->rcvbuf, count);
@@ -251,7 +253,8 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
				cs->tx_skb = NULL;
				cs->tx_skb = NULL;
			}
			}
		}
		}
		if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
		cs->tx_skb = skb_dequeue(&cs->sq);
		if (cs->tx_skb) {
			cs->tx_cnt = 0;
			cs->tx_cnt = 0;
			isac_fill_fifo(cs);
			isac_fill_fifo(cs);
		} else
		} else
@@ -313,7 +316,8 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
#if ARCOFI_USE
#if ARCOFI_USE
			if (v1 & 0x08) {
			if (v1 & 0x08) {
				if (!cs->dc.isac.mon_rx) {
				if (!cs->dc.isac.mon_rx) {
					if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
					cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
					if (!cs->dc.isac.mon_rx) {
						if (cs->debug & L1_DEB_WARN)
						if (cs->debug & L1_DEB_WARN)
							debugl1(cs, "ISAC MON RX out of memory!");
							debugl1(cs, "ISAC MON RX out of memory!");
						cs->dc.isac.mocr &= 0xf0;
						cs->dc.isac.mocr &= 0xf0;
@@ -343,7 +347,8 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
		afterMONR0:
		afterMONR0:
			if (v1 & 0x80) {
			if (v1 & 0x80) {
				if (!cs->dc.isac.mon_rx) {
				if (!cs->dc.isac.mon_rx) {
					if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
					cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
					if (!cs->dc.isac.mon_rx) {
						if (cs->debug & L1_DEB_WARN)
						if (cs->debug & L1_DEB_WARN)
							debugl1(cs, "ISAC MON RX out of memory!");
							debugl1(cs, "ISAC MON RX out of memory!");
						cs->dc.isac.mocr &= 0x0f;
						cs->dc.isac.mocr &= 0x0f;
+72 −13
Original line number Original line Diff line number Diff line
@@ -2264,6 +2264,57 @@ static void mv88e6xxx_bridge_work(struct work_struct *work)
	mutex_unlock(&ps->smi_mutex);
	mutex_unlock(&ps->smi_mutex);
}
}


static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
				     int reg, int val)
{
	int ret;

	ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
	if (ret < 0)
		goto restore_page_0;

	ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
restore_page_0:
	_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);

	return ret;
}

static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
				    int reg)
{
	int ret;

	ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
	if (ret < 0)
		goto restore_page_0;

	ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
restore_page_0:
	_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);

	return ret;
}

static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
{
	int ret;

	ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
				       MII_BMCR);
	if (ret < 0)
		return ret;

	if (ret & BMCR_PDOWN) {
		ret &= ~BMCR_PDOWN;
		ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
						PAGE_FIBER_SERDES, MII_BMCR,
						ret);
	}

	return ret;
}

static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
{
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -2367,6 +2418,23 @@ static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
			goto abort;
			goto abort;
	}
	}


	/* If this port is connected to a SerDes, make sure the SerDes is not
	 * powered down.
	 */
	if (mv88e6xxx_6352_family(ds)) {
		ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
		if (ret < 0)
			goto abort;
		ret &= PORT_STATUS_CMODE_MASK;
		if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
		    (ret == PORT_STATUS_CMODE_1000BASE_X) ||
		    (ret == PORT_STATUS_CMODE_SGMII)) {
			ret = mv88e6xxx_power_on_serdes(ds);
			if (ret < 0)
				goto abort;
		}
	}

	/* Port Control 2: don't force a good FCS, set the maximum frame size to
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
	 * untagged frames on this port, do a destination address lookup on all
	 * untagged frames on this port, do a destination address lookup on all
@@ -2714,13 +2782,9 @@ int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
	int ret;
	int ret;


	mutex_lock(&ps->smi_mutex);
	mutex_lock(&ps->smi_mutex);
	ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
	ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
	if (ret < 0)
		goto error;
	ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
error:
	_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
	mutex_unlock(&ps->smi_mutex);
	mutex_unlock(&ps->smi_mutex);

	return ret;
	return ret;
}
}


@@ -2731,14 +2795,9 @@ int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
	int ret;
	int ret;


	mutex_lock(&ps->smi_mutex);
	mutex_lock(&ps->smi_mutex);
	ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
	ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
	if (ret < 0)
		goto error;

	ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
error:
	_mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
	mutex_unlock(&ps->smi_mutex);
	mutex_unlock(&ps->smi_mutex);

	return ret;
	return ret;
}
}


+8 −0
Original line number Original line Diff line number Diff line
@@ -28,6 +28,10 @@
#define SMI_CMD_OP_45_READ_DATA_INC	((3 << 10) | SMI_CMD_BUSY)
#define SMI_CMD_OP_45_READ_DATA_INC	((3 << 10) | SMI_CMD_BUSY)
#define SMI_DATA		0x01
#define SMI_DATA		0x01


/* Fiber/SERDES Registers are located at SMI address F, page 1 */
#define REG_FIBER_SERDES	0x0f
#define PAGE_FIBER_SERDES	0x01

#define REG_PORT(p)		(0x10 + (p))
#define REG_PORT(p)		(0x10 + (p))
#define PORT_STATUS		0x00
#define PORT_STATUS		0x00
#define PORT_STATUS_PAUSE_EN	BIT(15)
#define PORT_STATUS_PAUSE_EN	BIT(15)
@@ -45,6 +49,10 @@
#define PORT_STATUS_MGMII	BIT(6) /* 6185 */
#define PORT_STATUS_MGMII	BIT(6) /* 6185 */
#define PORT_STATUS_TX_PAUSED	BIT(5)
#define PORT_STATUS_TX_PAUSED	BIT(5)
#define PORT_STATUS_FLOW_CTRL	BIT(4)
#define PORT_STATUS_FLOW_CTRL	BIT(4)
#define PORT_STATUS_CMODE_MASK	0x0f
#define PORT_STATUS_CMODE_100BASE_X	0x8
#define PORT_STATUS_CMODE_1000BASE_X	0x9
#define PORT_STATUS_CMODE_SGMII		0xa
#define PORT_PCS_CTRL		0x01
#define PORT_PCS_CTRL		0x01
#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK	BIT(15)
#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK	BIT(15)
#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK	BIT(14)
#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK	BIT(14)
+7 −3
Original line number Original line Diff line number Diff line
@@ -2653,7 +2653,7 @@ static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
	/* Write request msg to hwrm channel */
	/* Write request msg to hwrm channel */
	__iowrite32_copy(bp->bar0, data, msg_len / 4);
	__iowrite32_copy(bp->bar0, data, msg_len / 4);


	for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
	for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
		writel(0, bp->bar0 + i);
		writel(0, bp->bar0 + i);


	/* currently supports only one outstanding message */
	/* currently supports only one outstanding message */
@@ -3391,11 +3391,11 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
		struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
		struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
		struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
		struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;


		cpr->cp_doorbell = bp->bar1 + i * 0x80;
		rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
		rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
					      INVALID_STATS_CTX_ID);
					      INVALID_STATS_CTX_ID);
		if (rc)
		if (rc)
			goto err_out;
			goto err_out;
		cpr->cp_doorbell = bp->bar1 + i * 0x80;
		BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
		BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
		bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
		bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
	}
	}
@@ -3830,6 +3830,7 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp)
	struct hwrm_ver_get_input req = {0};
	struct hwrm_ver_get_input req = {0};
	struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
	struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;


	bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
	req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
	req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
	req.hwrm_intf_min = HWRM_VERSION_MINOR;
	req.hwrm_intf_min = HWRM_VERSION_MINOR;
@@ -3855,6 +3856,9 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp)
	if (!bp->hwrm_cmd_timeout)
	if (!bp->hwrm_cmd_timeout)
		bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
		bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;


	if (resp->hwrm_intf_maj >= 1)
		bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);

hwrm_ver_get_exit:
hwrm_ver_get_exit:
	mutex_unlock(&bp->hwrm_cmd_lock);
	mutex_unlock(&bp->hwrm_cmd_lock);
	return rc;
	return rc;
@@ -4555,7 +4559,7 @@ bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
		if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
		if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
			req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
			req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
		if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
		if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
			req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
			req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
		req->enables |=
		req->enables |=
			cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
			cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
	} else {
	} else {
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