[ARM] 4328/1: Move i.MX UART regs to driver (ff4bfb21) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/serial/imx.c

+205 −63

Original line number	Original line	Diff line number	Diff line
	@@ -46,6 +46,122 @@
	#include <asm/hardware.h>		#include <asm/hardware.h>
	#include <asm/arch/imx-uart.h>		#include <asm/arch/imx-uart.h>

			/* Register definitions */
			#define URXD0 0x0 /* Receiver Register */
			#define URTX0 0x40 /* Transmitter Register */
			#define UCR1 0x80 /* Control Register 1 */
			#define UCR2 0x84 /* Control Register 2 */
			#define UCR3 0x88 /* Control Register 3 */
			#define UCR4 0x8c /* Control Register 4 */
			#define UFCR 0x90 /* FIFO Control Register */
			#define USR1 0x94 /* Status Register 1 */
			#define USR2 0x98 /* Status Register 2 */
			#define UESC 0x9c /* Escape Character Register */
			#define UTIM 0xa0 /* Escape Timer Register */
			#define UBIR 0xa4 /* BRM Incremental Register */
			#define UBMR 0xa8 /* BRM Modulator Register */
			#define UBRC 0xac /* Baud Rate Count Register */
			#define BIPR1 0xb0 /* Incremental Preset Register 1 */
			#define BIPR2 0xb4 /* Incremental Preset Register 2 */
			#define BIPR3 0xb8 /* Incremental Preset Register 3 */
			#define BIPR4 0xbc /* Incremental Preset Register 4 */
			#define BMPR1 0xc0 /* BRM Modulator Register 1 */
			#define BMPR2 0xc4 /* BRM Modulator Register 2 */
			#define BMPR3 0xc8 /* BRM Modulator Register 3 */
			#define BMPR4 0xcc /* BRM Modulator Register 4 */
			#define UTS 0xd0 /* UART Test Register */

			/* UART Control Register Bit Fields.*/
			#define URXD_CHARRDY (1<<15)
			#define URXD_ERR (1<<14)
			#define URXD_OVRRUN (1<<13)
			#define URXD_FRMERR (1<<12)
			#define URXD_BRK (1<<11)
			#define URXD_PRERR (1<<10)
			#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
			#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
			#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
			#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
			#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
			#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
			#define UCR1_IREN (1<<7) /* Infrared interface enable */
			#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
			#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
			#define UCR1_SNDBRK (1<<4) /* Send break */
			#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
			#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
			#define UCR1_DOZE (1<<1) /* Doze */
			#define UCR1_UARTEN (1<<0) /* UART enabled */
			#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
			#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
			#define UCR2_CTSC (1<<13) /* CTS pin control */
			#define UCR2_CTS (1<<12) /* Clear to send */
			#define UCR2_ESCEN (1<<11) /* Escape enable */
			#define UCR2_PREN (1<<8) /* Parity enable */
			#define UCR2_PROE (1<<7) /* Parity odd/even */
			#define UCR2_STPB (1<<6) /* Stop */
			#define UCR2_WS (1<<5) /* Word size */
			#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
			#define UCR2_TXEN (1<<2) /* Transmitter enabled */
			#define UCR2_RXEN (1<<1) /* Receiver enabled */
			#define UCR2_SRST (1<<0) /* SW reset */
			#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
			#define UCR3_PARERREN (1<<12) /* Parity enable */
			#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
			#define UCR3_DSR (1<<10) /* Data set ready */
			#define UCR3_DCD (1<<9) /* Data carrier detect */
			#define UCR3_RI (1<<8) /* Ring indicator */
			#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
			#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
			#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
			#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
			#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
			#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
			#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
			#define UCR3_BPEN (1<<0) /* Preset registers enable */
			#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
			#define UCR4_INVR (1<<9) /* Inverted infrared reception */
			#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
			#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
			#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
			#define UCR4_IRSC (1<<5) /* IR special case */
			#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
			#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
			#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
			#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
			#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
			#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
			#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
			#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
			#define USR1_RTSS (1<<14) /* RTS pin status */
			#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
			#define USR1_RTSD (1<<12) /* RTS delta */
			#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
			#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
			#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
			#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
			#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
			#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
			#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
			#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
			#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
			#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
			#define USR2_IDLE (1<<12) /* Idle condition */
			#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
			#define USR2_WAKE (1<<7) /* Wake */
			#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
			#define USR2_TXDC (1<<3) /* Transmitter complete */
			#define USR2_BRCD (1<<2) /* Break condition */
			#define USR2_ORE (1<<1) /* Overrun error */
			#define USR2_RDR (1<<0) /* Recv data ready */
			#define UTS_FRCPERR (1<<13) /* Force parity error */
			#define UTS_LOOP (1<<12) /* Loop tx and rx */
			#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
			#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
			#define UTS_TXFULL (1<<4) /* TxFIFO full */
			#define UTS_RXFULL (1<<3) /* RxFIFO full */
			#define UTS_SOFTRST (1<<0) /* Software reset */

	/* We've been assigned a range on the "Low-density serial ports" major */		/* We've been assigned a range on the "Low-density serial ports" major */
	#define SERIAL_IMX_MAJOR 204		#define SERIAL_IMX_MAJOR 204
	#define MINOR_START 41		#define MINOR_START 41
	@@ -128,7 +244,10 @@ static void imx_timeout(unsigned long data)
	static void imx_stop_tx(struct uart_port *port)		static void imx_stop_tx(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	UCR1((u32)sport->port.membase) &= ~UCR1_TXMPTYEN;		unsigned long temp;

			temp = readl(sport->port.membase + UCR1);
			writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
	}		}

	/*		/*
	@@ -137,7 +256,10 @@ static void imx_stop_tx(struct uart_port *port)
	static void imx_stop_rx(struct uart_port *port)		static void imx_stop_rx(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	UCR2((u32)sport->port.membase) &= ~UCR2_RXEN;		unsigned long temp;

			temp = readl(sport->port.membase + UCR2);
			writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
	}		}

	/*		/*
	@@ -154,10 +276,10 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
	{		{
	struct circ_buf *xmit = &sport->port.info->xmit;		struct circ_buf *xmit = &sport->port.info->xmit;

	while (!(UTS((u32)sport->port.membase) & UTS_TXFULL)) {		while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
	/* send xmit->buf[xmit->tail]		/* send xmit->buf[xmit->tail]
	* out the port here */		* out the port here */
	URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail];		writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
	xmit->tail = (xmit->tail + 1) &		xmit->tail = (xmit->tail + 1) &
	(UART_XMIT_SIZE - 1);		(UART_XMIT_SIZE - 1);
	sport->port.icount.tx++;		sport->port.icount.tx++;
	@@ -175,21 +297,24 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
	static void imx_start_tx(struct uart_port *port)		static void imx_start_tx(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
			unsigned long temp;

	UCR1((u32)sport->port.membase) \|= UCR1_TXMPTYEN;		temp = readl(sport->port.membase + UCR1);
			writel(temp \| UCR1_TXMPTYEN, sport->port.membase + UCR1);

			if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
	imx_transmit_buffer(sport);		imx_transmit_buffer(sport);
	}		}

	static irqreturn_t imx_rtsint(int irq, void *dev_id)		static irqreturn_t imx_rtsint(int irq, void *dev_id)
	{		{
	struct imx_port sport = (struct imx_port )dev_id;		struct imx_port sport = (struct imx_port )dev_id;
	unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS;		unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
	unsigned long flags;		unsigned long flags;

	spin_lock_irqsave(&sport->port.lock, flags);		spin_lock_irqsave(&sport->port.lock, flags);

	USR1((u32)sport->port.membase) = USR1_RTSD;		writel(USR1_RTSD, sport->port.membase + USR1);
	uart_handle_cts_change(&sport->port, !!val);		uart_handle_cts_change(&sport->port, !!val);
	wake_up_interruptible(&sport->port.info->delta_msr_wait);		wake_up_interruptible(&sport->port.info->delta_msr_wait);

	@@ -207,7 +332,7 @@ static irqreturn_t imx_txint(int irq, void *dev_id)
	if (sport->port.x_char)		if (sport->port.x_char)
	{		{
	/* Send next char */		/* Send next char */
	URTX0((u32)sport->port.membase) = sport->port.x_char;		writel(sport->port.x_char, sport->port.membase + URTX0);
	goto out;		goto out;
	}		}

	@@ -231,17 +356,18 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
	struct imx_port *sport = dev_id;		struct imx_port *sport = dev_id;
	unsigned int rx,flg,ignored = 0;		unsigned int rx,flg,ignored = 0;
	struct tty_struct *tty = sport->port.info->tty;		struct tty_struct *tty = sport->port.info->tty;
	unsigned long flags;		unsigned long flags, temp;

	rx = URXD0((u32)sport->port.membase);		rx = readl(sport->port.membase + URXD0);
	spin_lock_irqsave(&sport->port.lock,flags);		spin_lock_irqsave(&sport->port.lock,flags);

	do {		do {
	flg = TTY_NORMAL;		flg = TTY_NORMAL;
	sport->port.icount.rx++;		sport->port.icount.rx++;

	if( USR2((u32)sport->port.membase) & USR2_BRCD ) {		temp = readl(sport->port.membase + USR2);
	USR2((u32)sport->port.membase) \|= USR2_BRCD;		if( temp & USR2_BRCD ) {
			writel(temp \| USR2_BRCD, sport->port.membase + USR2);
	if(uart_handle_break(&sport->port))		if(uart_handle_break(&sport->port))
	goto ignore_char;		goto ignore_char;
	}		}
	@@ -257,7 +383,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
	tty_insert_flip_char(tty, rx, flg);		tty_insert_flip_char(tty, rx, flg);

	ignore_char:		ignore_char:
	rx = URXD0((u32)sport->port.membase);		rx = readl(sport->port.membase + URXD0);
	} while(rx & URXD_CHARRDY);		} while(rx & URXD_CHARRDY);

	out:		out:
	@@ -301,7 +427,7 @@ static unsigned int imx_tx_empty(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;

	return USR2((u32)sport->port.membase) & USR2_TXDC ? TIOCSER_TEMT : 0;		return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
	}		}

	/*		/*
	@@ -312,10 +438,10 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	unsigned int tmp = TIOCM_DSR \| TIOCM_CAR;		unsigned int tmp = TIOCM_DSR \| TIOCM_CAR;

	if (USR1((u32)sport->port.membase) & USR1_RTSS)		if (readl(sport->port.membase + USR1) & USR1_RTSS)
	tmp \|= TIOCM_CTS;		tmp \|= TIOCM_CTS;

	if (UCR2((u32)sport->port.membase) & UCR2_CTS)		if (readl(sport->port.membase + UCR2) & UCR2_CTS)
	tmp \|= TIOCM_RTS;		tmp \|= TIOCM_RTS;

	return tmp;		return tmp;
	@@ -324,11 +450,14 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
	static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)		static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
			unsigned long temp;

			temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;

	if (mctrl & TIOCM_RTS)		if (mctrl & TIOCM_RTS)
	UCR2((u32)sport->port.membase) \|= UCR2_CTS;		temp \|= UCR2_CTS;
	else
	UCR2((u32)sport->port.membase) &= ~UCR2_CTS;		writel(temp, sport->port.membase + UCR2);
	}		}

	/*		/*
	@@ -337,14 +466,16 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
	static void imx_break_ctl(struct uart_port *port, int break_state)		static void imx_break_ctl(struct uart_port *port, int break_state)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	unsigned long flags;		unsigned long flags, temp;

	spin_lock_irqsave(&sport->port.lock, flags);		spin_lock_irqsave(&sport->port.lock, flags);

			temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;

	if ( break_state != 0 )		if ( break_state != 0 )
	UCR1((u32)sport->port.membase) \|= UCR1_SNDBRK;		temp \|= UCR1_SNDBRK;
	else
	UCR1((u32)sport->port.membase) &= ~UCR1_SNDBRK;		writel(temp, sport->port.membase + UCR1);

	spin_unlock_irqrestore(&sport->port.lock, flags);		spin_unlock_irqrestore(&sport->port.lock, flags);
	}		}
	@@ -373,7 +504,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)

	val \|= UFCR_RFDIV & (ufcr_rfdiv << 7);		val \|= UFCR_RFDIV & (ufcr_rfdiv << 7);

	UFCR((u32)sport->port.membase) = val;		writel(val, sport->port.membase + UFCR);

	return 0;		return 0;
	}		}
	@@ -382,14 +513,15 @@ static int imx_startup(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	int retval;		int retval;
	unsigned long flags;		unsigned long flags, temp;

	imx_setup_ufcr(sport, 0);		imx_setup_ufcr(sport, 0);

	/* disable the DREN bit (Data Ready interrupt enable) before		/* disable the DREN bit (Data Ready interrupt enable) before
	* requesting IRQs		* requesting IRQs
	*/		*/
	UCR4((u32)sport->port.membase) &= ~UCR4_DREN;		temp = readl(sport->port.membase + UCR4);
			writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);

	/*		/*
	* Allocate the IRQ		* Allocate the IRQ
	@@ -411,12 +543,16 @@ static int imx_startup(struct uart_port *port)
	/*		/*
	* Finally, clear and enable interrupts		* Finally, clear and enable interrupts
	*/		*/
			writel(USR1_RTSD, sport->port.membase + USR1);

			temp = readl(sport->port.membase + UCR1);
			temp \|= (UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN \| UCR1_UARTEN);
			writel(temp, sport->port.membase + UCR1);

	USR1((u32)sport->port.membase) = USR1_RTSD;		temp = readl(sport->port.membase + UCR2);
	UCR1((u32)sport->port.membase) \|=		temp \|= (UCR2_RXEN \| UCR2_TXEN);
	(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN \| UCR1_UARTEN);		writel(temp, sport->port.membase + UCR2);

	UCR2((u32)sport->port.membase) \|= (UCR2_RXEN \| UCR2_TXEN);
	/*		/*
	* Enable modem status interrupts		* Enable modem status interrupts
	*/		*/
	@@ -437,6 +573,7 @@ static int imx_startup(struct uart_port *port)
	static void imx_shutdown(struct uart_port *port)		static void imx_shutdown(struct uart_port *port)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
			unsigned long temp;

	/*		/*
	* Stop our timer.		* Stop our timer.
	@@ -454,8 +591,9 @@ static void imx_shutdown(struct uart_port *port)
	* Disable all interrupts, port and break condition.		* Disable all interrupts, port and break condition.
	*/		*/

	UCR1((u32)sport->port.membase) &=		temp = readl(sport->port.membase + UCR1);
	~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN \| UCR1_UARTEN);		temp &= ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN \| UCR1_UARTEN);
			writel(temp, sport->port.membase + UCR1);
	}		}

	static void		static void
	@@ -548,18 +686,18 @@ imx_set_termios(struct uart_port port, struct ktermios termios,
	/*		/*
	* disable interrupts and drain transmitter		* disable interrupts and drain transmitter
	*/		*/
	old_ucr1 = UCR1((u32)sport->port.membase);		old_ucr1 = readl(sport->port.membase + UCR1);
	UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN);		writel(old_ucr1 & ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN),
			sport->port.membase + UCR1);

	while ( !(USR2((u32)sport->port.membase) & USR2_TXDC))		while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
	barrier();		barrier();

	/* then, disable everything */		/* then, disable everything */
	old_txrxen = UCR2((u32)sport->port.membase) & ( UCR2_TXEN \| UCR2_RXEN );		old_txrxen = readl(sport->port.membase + UCR2);
	UCR2((u32)sport->port.membase) &= ~( UCR2_TXEN \| UCR2_RXEN);		writel(old_txrxen & ~( UCR2_TXEN \| UCR2_RXEN),
			sport->port.membase + UCR2);
	/* set the parity, stop bits and data size */		old_txrxen &= (UCR2_TXEN \| UCR2_RXEN);
	UCR2((u32)sport->port.membase) = ucr2;

	/* set the baud rate. We assume uartclk = 16 MHz		/* set the baud rate. We assume uartclk = 16 MHz
	*		*
	@@ -567,11 +705,13 @@ imx_set_termios(struct uart_port port, struct ktermios termios,
	* --------- = --------		* --------- = --------
	* uartclk UBMR - 1		* uartclk UBMR - 1
	*/		*/
	UBIR((u32)sport->port.membase) = (baud / 100) - 1;		writel((baud / 100) - 1, sport->port.membase + UBIR);
	UBMR((u32)sport->port.membase) = 10000 - 1;		writel(10000 - 1, sport->port.membase + UBMR);

			writel(old_ucr1, sport->port.membase + UCR1);

	UCR1((u32)sport->port.membase) = old_ucr1;		/* set the parity, stop bits and data size */
	UCR2((u32)sport->port.membase) \|= old_txrxen;		writel(ucr2 \| old_txrxen, sport->port.membase + UCR2);

	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))		if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
	imx_enable_ms(&sport->port);		imx_enable_ms(&sport->port);
	@@ -730,9 +870,11 @@ static void __init imx_init_ports(void)
	static void imx_console_putchar(struct uart_port *port, int ch)		static void imx_console_putchar(struct uart_port *port, int ch)
	{		{
	struct imx_port sport = (struct imx_port )port;		struct imx_port sport = (struct imx_port )port;
	while ((UTS((u32)sport->port.membase) & UTS_TXFULL))
			while (readl(sport->port.membase + UTS) & UTS_TXFULL)
	barrier();		barrier();
	URTX0((u32)sport->port.membase) = ch;
			writel(ch, sport->port.membase + URTX0);
	}		}

	/*		/*
	@@ -747,13 +889,14 @@ imx_console_write(struct console co, const char s, unsigned int count)
	/*		/*
	* First, save UCR1/2 and then disable interrupts		* First, save UCR1/2 and then disable interrupts
	*/		*/
	old_ucr1 = UCR1((u32)sport->port.membase);		old_ucr1 = readl(sport->port.membase + UCR1);
	old_ucr2 = UCR2((u32)sport->port.membase);		old_ucr2 = readl(sport->port.membase + UCR2);

	UCR1((u32)sport->port.membase) =		writel((old_ucr1 \| UCR1_UARTCLKEN \| UCR1_UARTEN) &
	(old_ucr1 \| UCR1_UARTCLKEN \| UCR1_UARTEN)		~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN),
	& ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN);		sport->port.membase + UCR1);
	UCR2((u32)sport->port.membase) = old_ucr2 \| UCR2_TXEN;
			writel(old_ucr2 \| UCR2_TXEN, sport->port.membase + UCR2);

	uart_console_write(&sport->port, s, count, imx_console_putchar);		uart_console_write(&sport->port, s, count, imx_console_putchar);

	@@ -761,10 +904,10 @@ imx_console_write(struct console co, const char s, unsigned int count)
	* Finally, wait for transmitter to become empty		* Finally, wait for transmitter to become empty
	* and restore UCR1/2		* and restore UCR1/2
	*/		*/
	while (!(USR2((u32)sport->port.membase) & USR2_TXDC));		while (!(readl(sport->port.membase + USR2) & USR2_TXDC));

	UCR1((u32)sport->port.membase) = old_ucr1;		writel(old_ucr1, sport->port.membase + UCR1);
	UCR2((u32)sport->port.membase) = old_ucr2;		writel(old_ucr2, sport->port.membase + UCR2);
	}		}

	/*		/*
	@@ -776,13 +919,13 @@ imx_console_get_options(struct imx_port sport, int baud,
	int parity, int bits)		int parity, int bits)
	{		{

	if ( UCR1((u32)sport->port.membase) \| UCR1_UARTEN ) {		if ( readl(sport->port.membase + UCR1) \| UCR1_UARTEN ) {
	/* ok, the port was enabled */		/* ok, the port was enabled */
	unsigned int ucr2, ubir,ubmr, uartclk;		unsigned int ucr2, ubir,ubmr, uartclk;
	unsigned int baud_raw;		unsigned int baud_raw;
	unsigned int ucfr_rfdiv;		unsigned int ucfr_rfdiv;

	ucr2 = UCR2((u32)sport->port.membase);		ucr2 = readl(sport->port.membase + UCR2);

	*parity = 'n';		*parity = 'n';
	if (ucr2 & UCR2_PREN) {		if (ucr2 & UCR2_PREN) {
	@@ -797,11 +940,10 @@ imx_console_get_options(struct imx_port sport, int baud,
	else		else
	*bits = 7;		*bits = 7;

	ubir = UBIR((u32)sport->port.membase) & 0xffff;		ubir = readl(sport->port.membase + UBIR) & 0xffff;
	ubmr = UBMR((u32)sport->port.membase) & 0xffff;		ubmr = readl(sport->port.membase + UBMR) & 0xffff;


	ucfr_rfdiv = (UFCR((u32)sport->port.membase) & UFCR_RFDIV) >> 7;		ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
	if (ucfr_rfdiv == 6)		if (ucfr_rfdiv == 6)
	ucfr_rfdiv = 7;		ucfr_rfdiv = 7;
	else		else

include/asm-arm/arch-imx/imx-regs.h

+0 −118

Original line number	Original line	Diff line number	Diff line
	@@ -477,122 +477,4 @@
	#define LCDISR_EOF (1<<1)		#define LCDISR_EOF (1<<1)
	#define LCDISR_BOF (1<<0)		#define LCDISR_BOF (1<<0)

	/*
	* UART Module. Takes the UART base address as argument
	*/
	#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
	#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
	#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
	#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
	#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
	#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
	#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
	#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
	#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
	#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
	#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
	#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
	#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
	#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
	#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
	#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
	#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
	#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
	#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
	#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
	#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
	#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
	#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */

	/* UART Control Register Bit Fields.*/
	#define URXD_CHARRDY (1<<15)
	#define URXD_ERR (1<<14)
	#define URXD_OVRRUN (1<<13)
	#define URXD_FRMERR (1<<12)
	#define URXD_BRK (1<<11)
	#define URXD_PRERR (1<<10)
	#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
	#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
	#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
	#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
	#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
	#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
	#define UCR1_IREN (1<<7) /* Infrared interface enable */
	#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
	#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
	#define UCR1_SNDBRK (1<<4) /* Send break */
	#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
	#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
	#define UCR1_DOZE (1<<1) /* Doze */
	#define UCR1_UARTEN (1<<0) /* UART enabled */
	#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
	#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
	#define UCR2_CTSC (1<<13) /* CTS pin control */
	#define UCR2_CTS (1<<12) /* Clear to send */
	#define UCR2_ESCEN (1<<11) /* Escape enable */
	#define UCR2_PREN (1<<8) /* Parity enable */
	#define UCR2_PROE (1<<7) /* Parity odd/even */
	#define UCR2_STPB (1<<6) /* Stop */
	#define UCR2_WS (1<<5) /* Word size */
	#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
	#define UCR2_TXEN (1<<2) /* Transmitter enabled */
	#define UCR2_RXEN (1<<1) /* Receiver enabled */
	#define UCR2_SRST (1<<0) /* SW reset */
	#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
	#define UCR3_PARERREN (1<<12) /* Parity enable */
	#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
	#define UCR3_DSR (1<<10) /* Data set ready */
	#define UCR3_DCD (1<<9) /* Data carrier detect */
	#define UCR3_RI (1<<8) /* Ring indicator */
	#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
	#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
	#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
	#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
	#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
	#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
	#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
	#define UCR3_BPEN (1<<0) /* Preset registers enable */
	#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
	#define UCR4_INVR (1<<9) /* Inverted infrared reception */
	#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
	#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
	#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
	#define UCR4_IRSC (1<<5) /* IR special case */
	#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
	#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
	#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
	#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
	#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
	#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
	#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
	#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
	#define USR1_RTSS (1<<14) /* RTS pin status */
	#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
	#define USR1_RTSD (1<<12) /* RTS delta */
	#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
	#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
	#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
	#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
	#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
	#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
	#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
	#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
	#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
	#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
	#define USR2_IDLE (1<<12) /* Idle condition */
	#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
	#define USR2_WAKE (1<<7) /* Wake */
	#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
	#define USR2_TXDC (1<<3) /* Transmitter complete */
	#define USR2_BRCD (1<<2) /* Break condition */
	#define USR2_ORE (1<<1) /* Overrun error */
	#define USR2_RDR (1<<0) /* Recv data ready */
	#define UTS_FRCPERR (1<<13) /* Force parity error */
	#define UTS_LOOP (1<<12) /* Loop tx and rx */
	#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
	#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
	#define UTS_TXFULL (1<<4) /* TxFIFO full */
	#define UTS_RXFULL (1<<3) /* RxFIFO full */
	#define UTS_SOFTRST (1<<0) /* Software reset */

	#endif // _IMX_REGS_H		#endif // _IMX_REGS_H