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Commit febdfbd2 authored by James Bottomley's avatar James Bottomley
Browse files

Merge tag '4.4-scsi-mkp' into misc 



SCSI queue for 4.4.

Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents 0da39687 2c5d16d6

Documentation/devicetree/bindings/ufs/ufs-qcom.txt

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+58 −0
Original line number Original line Diff line number Diff line 
* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY



UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.

Each UFS PHY node should have its own node.



To bind UFS PHY with UFS host controller, the controller node should

contain a phandle reference to UFS PHY node.



Required properties:

- compatible        : compatible list, contains "qcom,ufs-phy-qmp-20nm"

		      or "qcom,ufs-phy-qmp-14nm" according to the relevant phy in use.

- reg               : should contain PHY register address space (mandatory),

- reg-names         : indicates various resources passed to driver (via reg proptery) by name.

                      Required "reg-names" is "phy_mem".

- #phy-cells        : This property shall be set to 0

- vdda-phy-supply   : phandle to main PHY supply for analog domain

- vdda-pll-supply   : phandle to PHY PLL and Power-Gen block power supply

- clocks	    : List of phandle and clock specifier pairs

- clock-names       : List of clock input name strings sorted in the same

		      order as the clocks property. "ref_clk_src", "ref_clk",

		      "tx_iface_clk" & "rx_iface_clk" are mandatory but

		      "ref_clk_parent" is optional



Optional properties:

- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply

- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply

- vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply

- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply

- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on



Example:



	ufsphy1: ufsphy@0xfc597000 {

		compatible = "qcom,ufs-phy-qmp-20nm";

		reg = <0xfc597000 0x800>;

		reg-names = "phy_mem";

		#phy-cells = <0>;

		vdda-phy-supply = <&pma8084_l4>;

		vdda-pll-supply = <&pma8084_l12>;

		vdda-phy-max-microamp = <50000>;

		vdda-pll-max-microamp = <1000>;

		clock-names = "ref_clk_src",

			"ref_clk_parent",

			"ref_clk",

			"tx_iface_clk",

			"rx_iface_clk";

		clocks = <&clock_rpm clk_ln_bb_clk>,

			<&clock_gcc clk_pcie_1_phy_ldo >,

			<&clock_gcc clk_ufs_phy_ldo>,

			<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,

			<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;

	};



	ufshc@0xfc598000 {

		...

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

	};

Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt

+10 −1
Original line number Original line Diff line number Diff line
@@ -4,11 +4,18 @@ UFSHC nodes are defined to describe on-chip UFS host controllers. 
Each UFS controller instance should have its own node.

Each UFS controller instance should have its own node.





Required properties:

Required properties:

- compatible        : compatible list, contains "jedec,ufs-1.1"

- compatible		: must contain "jedec,ufs-1.1", may also list one or more

					  of the following:

					  "qcom,msm8994-ufshc"

					  "qcom,msm8996-ufshc"

					  "qcom,ufshc"

- interrupts        : <interrupt mapping for UFS host controller IRQ>

- interrupts        : <interrupt mapping for UFS host controller IRQ>

- reg               : <registers mapping>

- reg               : <registers mapping>





Optional properties:

Optional properties:

- phys                  : phandle to UFS PHY node

- phy-names             : the string "ufsphy" when is found in a node, along

                          with "phys" attribute, provides phandle to UFS PHY node

- vdd-hba-supply        : phandle to UFS host controller supply regulator node

- vdd-hba-supply        : phandle to UFS host controller supply regulator node

- vcc-supply            : phandle to VCC supply regulator node

- vcc-supply            : phandle to VCC supply regulator node

- vccq-supply           : phandle to VCCQ supply regulator node

- vccq-supply           : phandle to VCCQ supply regulator node
@@ -54,4 +61,6 @@ Example: 
		clocks = <&core 0>, <&ref 0>, <&iface 0>;

		clocks = <&core 0>, <&ref 0>, <&iface 0>;

		clock-names = "core_clk", "ref_clk", "iface_clk";

		clock-names = "core_clk", "ref_clk", "iface_clk";

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

	};
 
	};

drivers/message/fusion/mptctl.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -1038,6 +1038,10 @@ kbuf_alloc_2_sgl(int bytes, u32 sgdir, int sge_offset, int *frags, 
	int		 i, buflist_ent;

	int		 i, buflist_ent;

	int		 sg_spill = MAX_FRAGS_SPILL1;

	int		 sg_spill = MAX_FRAGS_SPILL1;

	int		 dir;

	int		 dir;



	if (bytes < 0)

		return NULL;



	/* initialization */

	/* initialization */

	*frags = 0;

	*frags = 0;

	*blp = NULL;

	*blp = NULL;

drivers/phy/phy-qcom-ufs.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -432,6 +432,7 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) 
out:

out:

	return ret;

	return ret;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_ref_clk);





static

static

int ufs_qcom_phy_disable_vreg(struct phy *phy,

int ufs_qcom_phy_disable_vreg(struct phy *phy,
@@ -474,6 +475,7 @@ void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy) 
		phy->is_ref_clk_enabled = false;

		phy->is_ref_clk_enabled = false;

	}

	}

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk);





#define UFS_REF_CLK_EN	(1 << 5)

#define UFS_REF_CLK_EN	(1 << 5)
@@ -517,11 +519,13 @@ void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy) 
{

{

	ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);

	ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk);





void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)

void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)

{

{

	ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);

	ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk);





/* Turn ON M-PHY RMMI interface clocks */

/* Turn ON M-PHY RMMI interface clocks */

int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)

int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
@@ -550,6 +554,7 @@ int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy) 
out:

out:

	return ret;

	return ret;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_iface_clk);





/* Turn OFF M-PHY RMMI interface clocks */

/* Turn OFF M-PHY RMMI interface clocks */

void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)

void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
@@ -562,6 +567,7 @@ void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy) 
		phy->is_iface_clk_enabled = false;

		phy->is_iface_clk_enabled = false;

	}

	}

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_iface_clk);





int ufs_qcom_phy_start_serdes(struct phy *generic_phy)

int ufs_qcom_phy_start_serdes(struct phy *generic_phy)

{

{
@@ -578,6 +584,7 @@ int ufs_qcom_phy_start_serdes(struct phy *generic_phy) 




	return ret;

	return ret;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes);





int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)

int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)

{

{
@@ -595,6 +602,7 @@ int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes) 




	return ret;

	return ret;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);





void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,

void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,

					  u8 major, u16 minor, u16 step)

					  u8 major, u16 minor, u16 step)
@@ -605,6 +613,7 @@ void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, 
	ufs_qcom_phy->host_ctrl_rev_minor = minor;

	ufs_qcom_phy->host_ctrl_rev_minor = minor;

	ufs_qcom_phy->host_ctrl_rev_step = step;

	ufs_qcom_phy->host_ctrl_rev_step = step;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);





int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)

int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)

{

{
@@ -625,6 +634,7 @@ int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) 




	return ret;

	return ret;

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy);





int ufs_qcom_phy_remove(struct phy *generic_phy,

int ufs_qcom_phy_remove(struct phy *generic_phy,

			struct ufs_qcom_phy *ufs_qcom_phy)

			struct ufs_qcom_phy *ufs_qcom_phy)
@@ -662,6 +672,7 @@ int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy) 
	return ufs_qcom_phy->phy_spec_ops->

	return ufs_qcom_phy->phy_spec_ops->

			is_physical_coding_sublayer_ready(ufs_qcom_phy);

			is_physical_coding_sublayer_ready(ufs_qcom_phy);

}

}

EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready);





int ufs_qcom_phy_power_on(struct phy *generic_phy)

int ufs_qcom_phy_power_on(struct phy *generic_phy)

{

{

drivers/scsi/Kconfig

+0 −1
Original line number Original line Diff line number Diff line
@@ -541,7 +541,6 @@ config SCSI_ARCMSR 




source "drivers/scsi/esas2r/Kconfig"

source "drivers/scsi/esas2r/Kconfig"

source "drivers/scsi/megaraid/Kconfig.megaraid"

source "drivers/scsi/megaraid/Kconfig.megaraid"

source "drivers/scsi/mpt2sas/Kconfig"

source "drivers/scsi/mpt3sas/Kconfig"

source "drivers/scsi/mpt3sas/Kconfig"

source "drivers/scsi/ufs/Kconfig"

source "drivers/scsi/ufs/Kconfig"