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Commit febae330 authored by Chandan Uddaraju's avatar Chandan Uddaraju Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: update clock entries to support cphy 



Add cphy specific clock entries for both the DSI
controller nodes.

Change-Id: I9694595cc079249ad2e4ed58d353f0cc8e3692e4
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 328e4eeb

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+16 −4
Original line number Original line Diff line number Diff line
@@ -446,10 +446,16 @@ 




		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "cphy_byte_clk0", "cphy_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1",

			      "cphy_byte_clk1", "cphy_pixel_clk1";





		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -495,10 +501,16 @@ 




		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "cphy_byte_clk0", "cphy_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1",

			      "cphy_byte_clk1", "cphy_pixel_clk1";





		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;

		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;