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Commit fe4ae21b authored by Jiong Wang's avatar Jiong Wang Committed by Greg Kroah-Hartman
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mips: bpf: fix encoding bug for mm_srlv32_op 



[ Upstream commit 17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428 ]

For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.

Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.

v1->v2:
  - Keep mm_srlv32_op sorted by value.

Fixes: f31318fd ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Acked-by: default avatarJakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: default avatarSong Liu <songliubraving@fb.com>
Signed-off-by: default avatarJiong Wang <jiong.wang@netronome.com>
Signed-off-by: default avatarAlexei Starovoitov <ast@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 43f93ca2

arch/mips/include/uapi/asm/inst.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -369,8 +369,8 @@ enum mm_32a_minor_op { 
	mm_ext_op = 0x02c,

	mm_ext_op = 0x02c,

	mm_pool32axf_op = 0x03c,

	mm_pool32axf_op = 0x03c,

	mm_srl32_op = 0x040,

	mm_srl32_op = 0x040,

	mm_srlv32_op = 0x050,

	mm_sra_op = 0x080,

	mm_sra_op = 0x080,

	mm_srlv32_op = 0x090,

	mm_rotr_op = 0x0c0,

	mm_rotr_op = 0x0c0,

	mm_lwxs_op = 0x118,

	mm_lwxs_op = 0x118,

	mm_addu32_op = 0x150,

	mm_addu32_op = 0x150,