Loading drivers/platform/msm/mhi_dev/mhi.c +24 −1 Original line number Diff line number Diff line Loading @@ -41,6 +41,9 @@ /* Wait time before suspend/resume is complete */ #define MHI_SUSPEND_MIN 100 #define MHI_SUSPEND_TIMEOUT 600 /* Wait time on the device for Host to set BHI_INTVEC */ #define MHI_BHI_INTVEC_MAX_CNT 200 #define MHI_BHI_INTVEC_WAIT_MS 50 #define MHI_WAKEUP_TIMEOUT_CNT 20 #define MHI_MASK_CH_EV_LEN 32 #define MHI_RING_CMD_ID 0 Loading Loading @@ -3162,7 +3165,7 @@ EXPORT_SYMBOL(mhi_dev_write_channel); static int mhi_dev_recover(struct mhi_dev *mhi) { int rc = 0; uint32_t syserr, max_cnt = 0, bhi_intvec = 0; uint32_t syserr, max_cnt = 0, bhi_intvec = 0, bhi_max_cnt = 0; u32 mhi_reset; enum mhi_dev_state state; Loading @@ -3187,6 +3190,26 @@ static int mhi_dev_recover(struct mhi_dev *mhi) if (rc) return rc; while (bhi_intvec == 0xffffffff && bhi_max_cnt < MHI_BHI_INTVEC_MAX_CNT) { /* Wait for Host to set the bhi_intvec */ msleep(MHI_BHI_INTVEC_WAIT_MS); mhi_log(MHI_MSG_VERBOSE, "Wait for Host to set BHI_INTVEC\n"); rc = mhi_dev_mmio_read(mhi, BHI_INTVEC, &bhi_intvec); if (rc) { pr_err("%s: Get BHI_INTVEC failed\n", __func__); return rc; } bhi_max_cnt++; } if (bhi_max_cnt == MHI_BHI_INTVEC_MAX_CNT) { mhi_log(MHI_MSG_ERROR, "Host failed to set BHI_INTVEC\n"); return -EINVAL; } if (bhi_intvec != 0xffffffff) { /* Indicate the host that the device is ready */ rc = ep_pcie_trigger_msi(mhi->phandle, bhi_intvec); Loading Loading
drivers/platform/msm/mhi_dev/mhi.c +24 −1 Original line number Diff line number Diff line Loading @@ -41,6 +41,9 @@ /* Wait time before suspend/resume is complete */ #define MHI_SUSPEND_MIN 100 #define MHI_SUSPEND_TIMEOUT 600 /* Wait time on the device for Host to set BHI_INTVEC */ #define MHI_BHI_INTVEC_MAX_CNT 200 #define MHI_BHI_INTVEC_WAIT_MS 50 #define MHI_WAKEUP_TIMEOUT_CNT 20 #define MHI_MASK_CH_EV_LEN 32 #define MHI_RING_CMD_ID 0 Loading Loading @@ -3162,7 +3165,7 @@ EXPORT_SYMBOL(mhi_dev_write_channel); static int mhi_dev_recover(struct mhi_dev *mhi) { int rc = 0; uint32_t syserr, max_cnt = 0, bhi_intvec = 0; uint32_t syserr, max_cnt = 0, bhi_intvec = 0, bhi_max_cnt = 0; u32 mhi_reset; enum mhi_dev_state state; Loading @@ -3187,6 +3190,26 @@ static int mhi_dev_recover(struct mhi_dev *mhi) if (rc) return rc; while (bhi_intvec == 0xffffffff && bhi_max_cnt < MHI_BHI_INTVEC_MAX_CNT) { /* Wait for Host to set the bhi_intvec */ msleep(MHI_BHI_INTVEC_WAIT_MS); mhi_log(MHI_MSG_VERBOSE, "Wait for Host to set BHI_INTVEC\n"); rc = mhi_dev_mmio_read(mhi, BHI_INTVEC, &bhi_intvec); if (rc) { pr_err("%s: Get BHI_INTVEC failed\n", __func__); return rc; } bhi_max_cnt++; } if (bhi_max_cnt == MHI_BHI_INTVEC_MAX_CNT) { mhi_log(MHI_MSG_ERROR, "Host failed to set BHI_INTVEC\n"); return -EINVAL; } if (bhi_intvec != 0xffffffff) { /* Indicate the host that the device is ready */ rc = ep_pcie_trigger_msi(mhi->phandle, bhi_intvec); Loading