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Commit fdab2afa authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add support for NPUCC driver for ATOLL 



Add support for network processing unit clock controller
found on ATOLL based devices. This will allow client driver
to probe and control their clocks.

Change-Id: Ibc5a169f09caeff83653ef208a3ce418aad5b2bf
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 62677b79

Documentation/devicetree/bindings/clock/qcom,npucc.txt

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding 


Required properties :

- compatible : must contain "qcom,npucc-sm8150" or "qcom,npucc-sm8150-v2"

		or "qcom,npucc-sdmmagpie".

		or "qcom,npucc-sdmmagpie" or "qcom,atoll-npucc".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

drivers/clk/qcom/Kconfig

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@@ -605,3 +605,11 @@ config SM_DISPCC_ATOLL 
	  ATOLL devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config SM_NPUCC_ATOLL

	tristate "ATOLL NPU Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the NPU clock controller on Qualcomm Technologies, Inc

	  ATOLL devices.

	  Say Y if you want to enable use of the Network Processing Unit.

drivers/clk/qcom/Makefile

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@@ -79,6 +79,7 @@ obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o 
obj-$(CONFIG_SM_GCC_ATOLL) += gcc-atoll.o

obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o

obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o

obj-$(CONFIG_SM_NPUCC_ATOLL) += npucc-atoll.o

obj-$(CONFIG_SM_VIDEOCC_ATOLL) += videocc-atoll.o

obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o

obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o

drivers/clk/qcom/npucc-atoll.c

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File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,npucc-atoll.h

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@@ -40,7 +40,7 @@ 
#define NPU_CC_RSC_XO_CLK					22

#define NPU_CC_S2P_CLK						23

#define NPU_CC_XO_CLK						24

#define NPU_CC_XO_CLK_SRC					25

#define NPU_DSP_CORE_CLK_SRC					25



/* NPU_CC resets */

#define NPU_CC_CAL_HM0_BCR					0